<sb0>
that board version was never made, but the midi/dmx is unchanged and should be correct on it
<mithro>
Okay - should I look at the R3 to be safe?
<mithro>
sb0: I also wanted to pick your brain about what type of "hardware module" you think would be good to support doing things like "programmable" cross-fades between two frame sources. I was thinking of a simple thing where you just write a little thing which lets you say something like "pixel a * y + pixel b * x, y++, x--"
<sb0>
R3 == R4 on midi and dmx afair
<sb0>
something like the pfpu I guess. but fixed point and higher throughput.
<mithro>
sb0: I'm guessing so - but I have no idea what the pfpu is :)
<sb0>
it's documented in my msc thesis
<mithro>
sb0: Okay, guess I should read up on that then?
<cr1901_modern>
something Floating Point Unit?
<GitHub35>
[migen] sbourdeauducq pushed 1 new commit to new: http://git.io/vnkEH
<mithro>
sb0: I'm a bit of a noob in this area, does this stuff relate to pixel shaders in GPUs?
<sb0>
yeah, a bit
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<cr1901_modern>
sb0: Have you thought about how to implement the VPI at all in the new simulator?
<cr1901_modern>
Or is this still down the road?
<mithro>
sb0: Thanks for all your help!
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<cr1901_modern>
sb0: Synthesis is currently broken in the new branch, at least if one takes advantage of automatic sys clock domain creation. The code generator adds a "reg platform_rst = 1'd1;". This is directly connected to sys_rst, which causes the compiler and PAR to optimize out everything
<sb0>
works here. are you sure it's not a problem with your code?
<cr1901_modern>
Yea, I'm thinking something's wrong with my code upon further inspection
<cr1901_modern>
not sure what. The clock is being optimized out regardless if I declared clk domains manually or not. And it worked before I started following new branch
<cr1901_modern>
I wonder if my mibuild file is screwed up...
<cr1901_modern>
For me, it's platform_rst <= platform_rst;
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<mithro>
sb0: you went to KTH on Stockholm?
<mithro>
sb0: I studied there for 6 months back in ~2005
<cr1901_modern>
I can't think of anything more relaxing on a Friday morning than trying to debug why Xilinx has decided to optimize my entire design away...
<mithro>
sb0: Well, I've read your masters thesis now :)
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<terpstra>
o.O I accidentally set my processor to an 8-way dcache... and it still met 125MHz timing closure