sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub26> [migen] enjoy-digital pushed 1 new commit to master: http://git.io/vnTjY
<GitHub26> migen/master e4329c7 Florent Kermarrec: actorlib/structuring: fix Pack in packetized mode...
<mithro> sb0: Do you know much about DMX and MIDI? I was looking at https://devel.rtems.org/browser/rtems/c/src/lib/libbsp/lm32/shared?order=name and pondering what we would need in an expansion board to interface with devices that support that
<sb0> midi needs (somewhat "fast") optos, dmx a rs485 transceiver
<sb0> you can look at the m1 schematics
<mithro> sb0: Is my best bet to just copy the m1 schematics?
<sb0> yes
<sb0> the latest ones
<mithro> sb0: okay - where there any "gotchas" that you hit that I should be aware of?
<sb0> opto speed
<sb0> those things are surprisingly slow
<sb0> lots of capacitance and all
<sb0> even at 30kHz there are problems
<whitequark> you can use ADuM series to avoid that
<whitequark> fast enough for 480mbps usb
<sb0> MIDI is designed to dump current into the diode of the receiving opto
<sb0> simplest is just to use an opto with the right characteristics.
<mithro> sb0: where do I find the schematics? https://github.com/m-labs/board-m1 right?
<sb0> that's the kicad version that was never completed, i'd look at the altium pdf on qi-hardware instead
<sb0> that board version was never made, but the midi/dmx is unchanged and should be correct on it
<mithro> Okay - should I look at the R3 to be safe?
<mithro> sb0: I also wanted to pick your brain about what type of "hardware module" you think would be good to support doing things like "programmable" cross-fades between two frame sources. I was thinking of a simple thing where you just write a little thing which lets you say something like "pixel a * y + pixel b * x, y++, x--"
<sb0> R3 == R4 on midi and dmx afair
<sb0> something like the pfpu I guess. but fixed point and higher throughput.
<mithro> sb0: I'm guessing so - but I have no idea what the pfpu is :)
<sb0> it's documented in my msc thesis
<mithro> sb0: Okay, guess I should read up on that then?
<cr1901_modern> something Floating Point Unit?
<GitHub35> [migen] sbourdeauducq pushed 1 new commit to new: http://git.io/vnkEH
<GitHub35> migen/new 0a55ef5 Sebastien Bourdeauducq: test: add divider
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<travis-ci> m-labs/migen#90 (new - 0a55ef5 : Sebastien Bourdeauducq): The build has errored.
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<mithro> sb0: I'm a bit of a noob in this area, does this stuff relate to pixel shaders in GPUs?
<sb0> yeah, a bit
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<cr1901_modern> sb0: Have you thought about how to implement the VPI at all in the new simulator?
<cr1901_modern> Or is this still down the road?
<mithro> sb0: Thanks for all your help!
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<cr1901_modern> sb0: Synthesis is currently broken in the new branch, at least if one takes advantage of automatic sys clock domain creation. The code generator adds a "reg platform_rst = 1'd1;". This is directly connected to sys_rst, which causes the compiler and PAR to optimize out everything
<sb0> works here. are you sure it's not a problem with your code?
<cr1901_modern> Yea, I'm thinking something's wrong with my code upon further inspection
<cr1901_modern> not sure what. The clock is being optimized out regardless if I declared clk domains manually or not. And it worked before I started following new branch
<cr1901_modern> I wonder if my mibuild file is screwed up...
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<cr1901_modern> sb0: https://gist.github.com/cr1901/639da8f7062e079e526c could you please do me a favor and run this gist on your computer, and tell me what line 23 of the output verilog says?
<cr1901_modern> For me, it's platform_rst <= platform_rst;
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<mithro> sb0: you went to KTH on Stockholm?
<mithro> sb0: I studied there for 6 months back in ~2005
<cr1901_modern> I can't think of anything more relaxing on a Friday morning than trying to debug why Xilinx has decided to optimize my entire design away...
<mithro> sb0: Well, I've read your masters thesis now :)
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<terpstra> o.O I accidentally set my processor to an 8-way dcache... and it still met 125MHz timing closure
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