sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<cr1901_modern> whitequark: Once I get PyQt up and running would you like me to send you .bat files I used to build it to be incorporated into conda (or alternatively do it myself)?
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<cr1901_modern> *FINALLY*, PyQt is installed
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<sb0> whitequark, what do you recommend for an ion gauge controller? I'm about to purchase a bunch of DC-DC converter modules, which together end up almost as expensive as second-hand controllers from ebay, but are guaranteed to arrive in 3 days, are very easy to use (unlike messing around with 50Hz transformers), and are flexible/hackable/debuggable (I don't have a lot of data on that chinese gauge I got)
<sb0> and arrive in working condition...
<sb0> hot cathode, btw
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<whitequark> sb0: I avoided the whole question by using an inverted magnetron gauge :)\
<whitequark> integrated controller, DC power, 0-10V analog output. no messing around whatsoever
<whitequark> btw I recommend getting that one. disregard "no test", the AIM gauge is practically impossible to destroy, and judging by the photos, it has not even seen many hours
<whitequark> well worth the cost
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<GitHub33> [artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/vCNtL
<GitHub33> artiq/master d7b4120 Sebastien Bourdeauducq: tools/short_format: display booleans directly
<GitHub33> artiq/master 661b9bf Sebastien Bourdeauducq: tools/short_format: increase max string length
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<sb0> seriously, asyncio's behaviour when writing on closed sockets is the most stupid thing ever
<sb0> do not raise an exception, just let the task continue and print error messages - without a proper backtrace - as if the user could do anything about that
<sb0> python 3.4 used to raise ConnectionResetError when you used drain(), 3.5 raises BrokenPipeError instead, and unreliably it seems
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<travis-ci> m-labs/artiq#519 (master - 661b9bf : Sebastien Bourdeauducq): The build passed.
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<GitHub94> [artiq] sbourdeauducq pushed 3 new commits to master: http://git.io/vCNOQ
<GitHub94> artiq/master 5947f54 Sebastien Bourdeauducq: pc_rpc: autotarget support
<GitHub94> artiq/master a560676 Sebastien Bourdeauducq: device_db: make target_name parameter optional for controllers
<GitHub94> artiq/master 03e3177 Sebastien Bourdeauducq: device_db: make best_effort parameter optional for controllers
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<travis-ci> m-labs/artiq#520 (master - 03e3177 : Sebastien Bourdeauducq): The build has errored.
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<wbx> hi
<wbx> i am interested in using lm32 arch. Is here anyone want to sell his milky one board?
<cr1901_modern> wbx: You don't really need a milkymist one board to play with lm32. MiSoC is capable of creating lm32 CPUs on a few devs boards like Pipistrello, Papilio Pro, etc
<cr1901_modern> And if you have about a week after work, you could port your own board if it's not available
<wbx> ah. i already merged lm32 uClibc support to uClibc-ng and elf2flt stuff into my repo. toolchain building is fine. now I try qemu-system-lm32. but I love real hardware for testing.
<wbx> cr1901_modern: i have no real skills in fpga stuff.
<wbx> cr1901_modern: what would be a simple solution for me, a soc for lm32 testing. I need ethernet.
<larsc> there are other more available boards with migen and lm32 support
<wbx> larsc: any link to some site where I could buy one?
<cr1901_modern> I don't think you're getting away with not learning how to play with FPGAs though :P
<cr1901_modern> _florent_: Any plans to merge in Arty support to Migen/MiSoC?
<wbx> I have some ready prepared Xilinx FPGA for Xtensa with a preloaded Bitstream.
<wbx> cr1901_modern: do you can suggest any book or docs for FPGA dummy's? :)
<cr1901_modern> wbx: http://www.fpga4fun.com/FPGAinfo1.html Read through all sections of this and you should be just fine.
<cr1901_modern> Including the "FPGA software" section
<cr1901_modern> You may find it useful to learn Verilog as well, or build your own digital circuits using pen and paper to "get a feel" of how things work
<cr1901_modern> But this is just me lol
<wbx> cr1901_modern: and the arty fpga would be good to start with lm32? I could reuse it for microblaze?
<cr1901_modern> I haven't actually used arty, but I THINK it should be big enough to comfortably house LM32 and address decoding for peripherals
<cr1901_modern> ping ysionneau
<larsc> fpgas are typically not bound to a specfic soft-cpu architecture
<larsc> you could even run lm32 and microblaze at the same time
<wbx> btw. can I just save my existing fpga bitstream on my xilinx kintex7? and reflash with lm32
<cr1901_modern> I do not know what kintex7 is, so I cannot help :(
<larsc> the kc705 can boot from SDcard if that is the board you have
<wbx> in general, can a fpga bitstream exported?
<wbx> or is it one way, just upload new stuff on the board.
<larsc> you don't have to export it, it's usually not stored in the FPGA itself, but on some time of external storage
<larsc> s/time/type/
<wbx> ah. so it is uploaded on every boot to the fpga.
<larsc> yes
<cr1901_modern> yes
<cr1901_modern> FPGAs are volatile in that regard
<wbx> just read it on fpga4fn ;)
<larsc> the storage in the fpga is volatile
<cr1901_modern> I don't see the point in exporting a bitstream. You can switch between multiple bitstreams; so for example, if you created a retro gaming system that can emulate multiple consoles, you could use a pushbutton to swap between FPGA consoles
<cr1901_modern> Xilinx explicitly supports this, but idk the details
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<wbx> cr1901_modern: i don't have the bitstream. I got it the boar for free, for xtensa stuff
<wbx> s/boar/for/g
<wbx> if I could reuse it for other architectures, it would be cool.
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<cr1901_modern> Oh... well. That's an interesting problem. Probably need to use JTAG to read out the bitstream from the flash chip (I would not know how to do this; my own exposure to JTAG was to use the RPi's GPIO as a shift register lol)
<wbx> last time I used JTAG was to recover a WRT54GS wth a self made parallel port cable ;)
<wbx> is anybody working on adding lm32 to the linux kernel?
<wbx> larsc: what happened to the port?
<larsc> got distracted with other stuff, I guess
<larsc> there was not much interest in it anyway
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<wbx> larsc: and lm engaged a company to do the port? th...
<larsc> Did they?
<wbx> larsc: but you wouldn't say the arch is deprecated?
<larsc> I mean the initial port was done by a company years ago
<larsc> but that was pretty crap and totaly buggy
<larsc> we rewrote pretty much all of it
<wbx> is lm32 usable for noMMU and MMU Linux?
<larsc> only nommu at the moment
<wbx> BFLT and FDPIC are supported?
<larsc> I only ever tested bflt
<wbx> good to know.
<wbx> i have seen some commits about FDPIC in the kernel git repo from m-labs.
<cr1901_modern> Well, there's also or1k, but I find lm32 code easier to read
<wbx> i am still a interested in the milky one. I am a collector of vintage embedded hardware :)
<cr1901_modern> Why not get something using an 80186 then :P?
<wbx> cr1901_modern: I played with or1k recently. qemu-system-or32 seems buggy, I can not boot a system.
<wbx> cr1901_modern: is it embedded? :P
<wbx> cr1901_modern: so no. just embedded, given up on old unix hardware ;)
<cr1901_modern> Sorry was afk. 80186 was an x86 variant meant for embedded use
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<wbx> cr1901_modern: oh. didn't know that. thought it was some x86 before i386 :)
<wbx> cr1901_modern: but I am concentrating on linux systems :)
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<wbx> cr1901_modern: do you have a milky one board?
<cr1901_modern> I do not :(. I didn't get involved in Migen/m-labs until April
<cr1901_modern> That was when I fell back in love with FPGAs after a three-year absence
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<cr1901_modern> sb0: the h5py IS a windows specific issue, just checked setup.py's output
<cr1901_modern> "Cannot access the file b/c it's locked by another process" bs
<sb0> where does this happen?
<cr1901_modern> I am figuring this out now. Windows probably didn't clean up properly when I CTRL+C'ed during setup.py during one attempt
<sb0> i think the master will start without h5py anyway. you just won't be able to start experiments.
<cr1901_modern> It doesn't, that's why I mentioned the error (without realizing it's most likely my fault and not anybody else's) :P
<sb0> hmm, where does it need it?
<cr1901_modern> line 9, worker_db.py
<sb0> ah right, there is "from artiq.master.worker_db import get_last_rid" in artiq_master.py
<sb0> and worker_db imports h5py
<sb0> if all else fails, you can probably just hack-add that function to artiq_master.py, though
<cr1901_modern> ack
<sb0> but is there a problem when installing with conda?
<cr1901_modern> yess, I'll put that in a gist in a sec
<sb0> well if it does break, open an issue
<sb0> did you source the py35 activate script?
<cr1901_modern> The Windows equivalent is "activate py35", so yes
<cr1901_modern> I also am running py35 in an environment where the path is fully cleared
<cr1901_modern> except for the default Windows provides, and llvm/Qt paths
<sb0> it seems the problem is, anaconda is not packaging h5py for windows and py35
<cr1901_modern> pip install h5py is failing b/c I don't have proper headers installed. Looking into it
<cr1901_modern> (Btw, do you want me to package PyQt and Qt 5 for Windows?)
<cr1901_modern> or just leave it to whitequark
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<travis-ci> m-labs/artiq#520 (master - 03e3177 : Sebastien Bourdeauducq): The build has errored.
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<ysionneau> wbx : yes the ARTY board can run lm32/microblaze/or1k. no DDR support yet though but it will come
<ysionneau> the support of the board is being written
<sb0> is there any reason why the arty port is not using the new branch?
<ysionneau> I dont think of any reason
<ysionneau> it will have to be updated upon switching to new branch
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<cr1901_modern> that reminds me: need to update n6502fpga b/c flen no longer exists
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<cr1901_modern> HDF5 fails to build on windows... at least on my machine. Will check later
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<wbx> ysionneau: no ddr support means no ram usage possible?
<wbx> ysionneau: can it be used to run linux on it?
<ysionneau> I never run linux on fpga boards, so I cannot help you with it
<ysionneau> but once DDR works on the ARTY, it should be able to boot Linux with mor1kx CPU
<ysionneau> or you can buy another cheap board like pipistrello which already has the DRAM working and can also run LM32/OR1K
<ysionneau> pipistrello port is more complete than ARTY one so far
<wbx> ysionneau: how long will it take to get DDR working?
<wbx> ysionneau: what os do you run on FPGA? or bare metal code only?
<ysionneau> I don't know, I won't be doing it
<ysionneau> you could ask _florent_ but I don't know if it's high in his priority list
<ysionneau> wbx: bare metal stuff
<larsc> wbx: sounds like an opportunity for a project to learn more about FPGAs and DDR memory
<wbx> larsc: I already ordered the ARTY in the evening, thought it could be a good board for FPGA hacking and understanding. ;)
<wbx> larsc: I would need to learn verilog for this?
<ysionneau> it's definetely a cool board
<ysionneau> you can already run code on it
<ysionneau> like the MiSoC BIOS
<ysionneau> using onchip ROM/RAM (blockRAM) instead of the on-board DDR
<ysionneau> there is lot to play with
<larsc> wbx: knowing how HDL works in general can't hurt for such a project
<ysionneau> ethernet and uart are working
<wbx> larsc: i have some colleagues at work, which are good in hardware related stuff. may be I can ask them to show me some stuff.
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