00:29 <cyrozap> What does it mean if I don't get any memtest errors during the ONEZERO and ZEROONE tests, but I get 262144 errors on the random data test and 4096 errors on the random write test?

00:31 <cyrozap> The PLL config that I've tested with is in here: https://github.com/cyrozap/misoc/blob/mimasv2-support-new/misoc/targets/mimasv2.py

00:47 <cr1901_modern> Bad address decoding?

01:39 <GitHub91> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vWbXJ

01:39 <GitHub91> artiq/master 32c95f2 Sebastien Bourdeauducq: worker: reduce some logging levels

01:47 <GitHub92> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vWb1w

01:47 <GitHub92> artiq/master f0eed11 Sebastien Bourdeauducq: protocols/pyon: improve error reporting of non-serializable type

01:51 <cyrozap> Oops, meant to say "4096 errors on the random *address* test"

01:56 <cr1901_modern> Again... bad address decoding :P?

02:00 <sb0> whitequark, will that install the bitstreams?

02:00 <sb0> https://github.com/m-labs/artiq/blob/master/doc/manual/installing.rst#installing-the-host-side-software

02:01 <travis-ci> m-labs/artiq#557 (master - 32c95f2 : Sebastien Bourdeauducq): The build passed.

02:01 <travis-ci> Build details : https://travis-ci.org/m-labs/artiq/builds/88028215

02:13 <cyrozap> cr1901_modern: I've checked all the pinouts and they seem correct, so I'm not sure where else it could be going wrong

02:15 <travis-ci> m-labs/artiq#558 (master - f0eed11 : Sebastien Bourdeauducq): The build passed.

02:15 <travis-ci> Build details : https://travis-ci.org/m-labs/artiq/builds/88028904

05:13 <mithro> sb0: so, flterm.py doesn't appear to work with my (probably broken) serial port, while flterm.c does

05:13 <mithro> sb0: it just dies with "serial.serialutil.SerialException: device reports readiness to read but returned no data (device disconnected or multiple access on port?)"

05:13 <sb0> mithro, haven't seen that ...

05:13 <sb0> _florent_, ?

05:14 <mithro> sb0: the serial port is probably broken, IE it is probably doing exactly what the above says - but it seems to work fine with flterm.c

07:18 <sb0> whitequark, i just received a chinese angle valve. even though it has a label that says "RIP OFF NO RETURN", it looks very good and was rather inexpensive.

07:19 <sb0> let me do a quick vac test...

07:33 <sb0> yeah it has no gross problems

07:35 <cr1901_modern> They couldn't have chosen a better void-warranty label statement. Unless it was in fact truth-in-advertising.

07:42 <sb0> oh, actually the crappy ball valve can probably be used to vent the small volume between the forepump and the angle valve

08:14 <_florent_> cyrozap: in memtest, you can add a print in hexa of the expected value and the read value

08:14 <_florent_> just keep the data test and reduce the size of the test

08:15 <_florent_> then if you see that data is swapped, you can try to play with clock phase or rd_bitslip and wr_bitslip

08:18 <cr1901_modern> Why would data be swapped if there was a bitslip? (I've never actually implemented a DRAM controller; it's on my todo list)

08:19 <cr1901_modern> Also _florent_, I know the minispartan6+ made poor design choices, but what's the maximum HDMI resolution it can do?

08:20 <_florent_> mithro: I never had that, it seems related to pyserial that is probably doing more checks than flterm

08:21 <cr1901_modern> s/made/was implemented with/

08:24 <_florent_> cr1901_modern: bitslip is on the iserdes and oserdes, but you have 16 serdes in //. You have to be sure the DRAM is sampling correcly your data: you adjust clk phase and wr_bitslip and that the FPGA is also sampling correctly the data returned from the DRAM: you adjust rd_bitslip

08:27 <_florent_> cr1903_modenr: it depends what you want to do with the minispartan6+ but you will be limited by the DRAM's bandwidth

08:29 <cr1901_modern> What's the bandwidth for minispartan? 75MHz clock, right?

08:30 <cr1901_modern> 1920*1080*60 is about 125MHz, which is only an estimate

08:31 <mithro> _florent_: yeah - I'm also getting a behavior with pyserial where data gets "stuck" in the incoming/outgoing buffers (don't really know how else to describe it)

08:31 <mithro> running the C version of flterm seems to cause it to flush

11:11 <cr1901_modern> You know what would be great? If MSYS's bash implementation didn't leak memory after its children died

12:24 <cr1901_modern> sb0: asyncio is new to me, especially in Python. Is it documented anywhere that asyncio imports Event()? https://github.com/m-labs/artiq/blob/master/artiq/frontend/artiq_gui.py#L51

15:27 <sb0> cr1901_modern, https://docs.python.org/3/library/asyncio-sync.html#event

15:27 <sb0> cr1901_modern, the widget itself should not use asyncio, I think

15:32 <sb0> http://www.ohwr.org/projects/ohr-meta/wiki/FOSDEM2016

16:57 <sb0> whitequark, can you close the "conda broken" issue?

16:57 <whitequark> sure

16:58 <sb0> thanks

16:58 <sb0> also, will this install the bitstreams:

16:58 <sb0> https://github.com/m-labs/artiq/blob/master/doc/manual/installing.rst#installing-the-host-side-software

17:00 <whitequark> no, and I'm fixing it right now

17:09 <whitequark> sb0: should we take the opportunity to teach good conda hygiene? e.g. maybe do something like

17:10 <whitequark> conda create -n $(date +conda-%Y-%m-%d) artiq-pipistrello-nist_qc1

17:11 <whitequark> and then tell to avoid upgrades and just create new environments instead so that rollback is possible?

19:46 <cr1901_modern> sb0: It doesn't/probably shouldn't. I just want a high-level overview on how the GUI code works before I start adding to it.

23:55 <cyrozap> _florent_: Thanks, that's a big help!