sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<sb0> cr1901_modern, is that loop from your code or the migen bug?
<sb0> if you're only using the basic features, you can try the simulator in the 'new' branch
<cr1901_modern> it's a "feature" with external Verilog code I'm linking against.
<cr1901_modern> Short version is that sometimes the address bus and data input bus of external code are combinationally connected. If data-in is rerouted to address bus out, and the new address is decoded by a different wishbone peripheral...
<cr1901_modern> well, bad things happen
<cr1901_modern> sb0: So what happens to actorlib, bus, etc. Do they become part of a separate library from misoc and migen?
<cr1901_modern> Not having to rewrite my own wishbone decoders came in handy when using migen
<sb0> the wishbone stuff will go to misoc
<cr1901_modern> Ahhh, and here I was thinking of making my own MIgen Supplementary Library and calling it MISL...
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<whitequark> cr1901_modern: urbit has zero technical merit. it's just pretentious obscurantism
<mithro> ysionneau: so apparently you may have added lm32 emulation to qemu?
<sb0> mithro, yes, Michael Walle did
<mithro> Michael Walle != ysionneau I'm assuming?
<sb0> yup
<mithro> lekernel == Michael Walle?
<sb0> no, lekernel is me
<sb0> Michael comes to this channel from time to time, used to be more often
<sb0> his nickname is mwalle
<sb0> or mw
<mithro> Oh - I didn't realise lekernel was you :P
<mithro> sb0: you also got uclinux running on the lm32 too right? I think I found a github repo from you with commits in about 2012....
<sb0> the port is lousy with bugs, but yeah
<mithro> Was the mmu addition to lm32 in misoc for trying to get real linux running?
<sb0> yes
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<cr1901_modern> whitequark: That was a beautiful explanation XD
<cr1901_modern> Well, and Net I believe. I guess ysionneau started with Net b/c the code base is easier for a hobbyist to port.
<cr1901_modern> mithro: and NetBSD requires a MMU as well
<mithro> cr1901_modern: why do I care about NetBSD? :P
<cr1901_modern> "mithro: Was the mmu addition to lm32 in misoc for trying to get real linux running?"
<mithro> cr1901_modern: ah :)
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<whitequark> have you seen http://www.veritygos.org/ ?
<whitequark> cc sb0 when he returns
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<cr1901_modern> God gtkwave's UI is horrible. I could deal with the crashes, if I didn't have to deal with the goddamn UI
<sb0> crashes?
<sb0> gtkwave is perhaps one of the 5 programs in the world that never crashed on me
<cr1901_modern> It crashes on some vcd files that I feed it from iverilog
<cr1901_modern> also please note that I run Windows, which is an afterthought in GNU land.
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<sb0> wtf
<cr1901_modern> I have a headache after trying to read that
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<whitequark> python is gross (and underspecified)
<GitHub4> [migen] sbourdeauducq pushed 7 new commits to new: http://git.io/vZVoO
<GitHub4> migen/new fa6d96b Sebastien Bourdeauducq: test/examples: do not attempt to run deleted examples
<GitHub4> migen/new 308c5d7 Sebastien Bourdeauducq: examples/graycounter: use new simulator
<GitHub4> migen/new 7bd72a1 Sebastien Bourdeauducq: sim: support clock domains without sync
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<travis-ci> m-labs/migen#80 (new - 047d1f4 : Sebastien Bourdeauducq): The build has errored.
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<sb0> please pay attention to such details
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<GitHub57> [migen] sbourdeauducq pushed 1 new commit to new: http://git.io/vZViy
<GitHub57> migen/new b43495a Sebastien Bourdeauducq: build/xilinx: minor cleanup
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<travis-ci> m-labs/migen#81 (new - b43495a : Sebastien Bourdeauducq): The build has errored.
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<eduardo__> Hello MiSOC and Migen Team. I just wanted to point you to the open source Lattice FPGA toolchain at http://www.clifford.at/icestorm/
<whitequark> we know.
<eduardo__> Did someone already of you use Migen as a frontend to Yosys?
<whitequark> yes, though not with icestorm
<sb0> haven't run it for a while though, so it's safe to assume it's broken
<eduardo__> ok, so i will put Migen as a potential frontend to yosys on our (not yet released) webpage (at least then someone will try to use migen as a frontend to Yosys to icestorm)
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<whitequark> oh, you're an icestorm dev? nice
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<sb0> and not sure if this function should be part of migen
<sb0> I'm also skeptical of the FlipFlop and Counter modules... instantiating and connecting them probably takes more code than integrating their functionality in the parent module
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<sb0> does reverse_bytes need to support the case when the signal width is not a multiple of 8?
<sb0> I cannot think of a sensible thing to do in this case
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<sb0> _florent_, "rst_n.eq(1 & ~rst)"? why the "1 &"?
<sb0> and why have an active low signal?
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<cr1901_modern> sb0: FWIW, I use the FlipFlop/Counter modules in my Migen code. I think perhaps there should be a "primitives" file
<cr1901_modern> a Counter and FlipFlop are two good candidates for primitive building blocks that I don't really want to type over and over again in new files
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<sb0> why would you use such modules when you can replace them with a single line of sync += ...?
<cr1901_modern> I meant WaitTimer, not Counter*. And for a flip-flop, well, it's nice that you can instantiate one of a desired width whose signals are self contained.
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<sb0> but you then need to connect those signals to something
<sb0> which takes more code than using the original signals directly
<cr1901_modern> hrm... :/ For me, it's a tradeoff between saving typing and encapsulating components. From my own experience, I favor multiple submodules over having a bunch of top-level signals.
<cr1901_modern> Which is probably part of my problem.
<sb0> a flipflop is not a component worth encapsulating
<sb0> if we have flipflop, what's next? adder?
<cr1901_modern> sure, why not? (no sarcasm)
<cr1901_modern> How would you quickly instantiate a register bank of flip-flops (not CSR)?
<sb0> self.sync += xxx in a for loop
<sb0> you have the same problem when connecting the signals of those FlipFlop modules
<cr1901_modern> Maybe I worry too much about encapsulation and that's why I haven't actually published any of my Migen code yet
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<cr1901_modern> anyways point taken. It's not like I'm going to forget how to make a flip-flop or counter in Migen. The encapsulation of a bunch of small components sounds appealing without thinking it through. :P
<sb0> you can also instantiate LUTs and FDs if you like
<cr1901_modern> FDs?
<sb0> the xilinx flipflop primitive
<sb0> post-synthesis
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<cr1901_modern> Ahhh... I've never actually used any of the special synthesis directives/primitives yet.
<cr1901_modern> In any case, I've checked out Migen's new branch, and will code against that from here on out. Don't really mind breaking my previous code.
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<sb0> migen.genlib.misc.reverse_bytes, migen.fhdl.bitcontainer.freversed ...
<cr1901_modern> It's like Perl, multiple ways to do the same thing :D
<cr1901_modern> Actually, what's going to happen to migen.flow?
<sb0> not sure yet
<cr1901_modern> I've never used it. I know _florent_ uses it heavily in his code, but it also seems like portions of migen.genlib serve the same purpose (fifo.py, for example)
<sb0> do you use it?
<cr1901_modern> ^^
<sb0> no
<cr1901_modern> I've been meaning to learn how to use it, but I was fine with genlib's fifo.py for my source/sink needs
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<_florent_> sb0: what is interesting in FlipFlop and Counter is of course not what is inside, but @ResetInserter() and @CEInserter()
<_florent_> sb0: if you don't want that modules, remove it I'll duplicate it in my cores.
<_florent_> sb0: for self.sync.por += rst_n.eq(1 & ~rst), flipflops are initialized to 0 at startup, that's why I'm using rst_n
<_florent_> sorry just passing by, have to go
<sb0> _florent_, is there any fpga where FFs cannot be initialized to 1 at startup?
<sb0> and this doesn't justify the "1&"
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<GitHub60> [migen] sbourdeauducq pushed 4 new commits to new: http://git.io/vZw3z
<GitHub60> migen/new 3367284 Sebastien Bourdeauducq: simplify imports, migen.fhdl.std -> migen
<GitHub60> migen/new 1bdb9be Sebastien Bourdeauducq: fhdl/decorators: remove deprecated API
<GitHub60> migen/new 9667d61 Sebastien Bourdeauducq: genlib: cleanup CRG
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<travis-ci> m-labs/migen#82 (new - eb921fb : Sebastien Bourdeauducq): The build has errored.
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<GitHub70> [migen] sbourdeauducq pushed 1 new commit to new: http://git.io/vZws4
<GitHub70> migen/new 42afba2 Sebastien Bourdeauducq: fhdl/decorators: remove traces of deprecated API
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<travis-ci> m-labs/migen#83 (new - 42afba2 : Sebastien Bourdeauducq): The build has errored.
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