sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<rjo>
using optree for multiplication it is a bit uncommon but i did like the tree implementation. it a makes the synthesizing/balancing job quite a bit easier and is very idiomatic. maybe reduce_tree(...) makes the name more pythonic.
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<sb0>
rjo, do you have a strong need/opinion in favor of optree?
<sb0>
nothing in migen/misoc/artiq uses it for multiplication
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<rjo>
i would keep it. maybe change the documentation and/or the name to contrast/compare it to functools.reduce()
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<GitHub32>
[migen] sbourdeauducq pushed 5 new commits to new: http://git.io/vZEZF
<GitHub32>
migen/new 714ae43 Sebastien Bourdeauducq: fhdl: remove features new simulator won't use
<cr1901_modern>
Finally found the cominatorial loop in my Migen code... only took me nearly two weeks (on and off, of course). Funny, viewing waveforms didn't help this time. Simulator's display_run=True option saved the day here. So thanks whoever implemented that lol
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<ysionneau>
I'll get back to you on this, do you have an email address where I can contact you?
<terpstra>
wesley@terpstra.ca
<terpstra>
(not my work email address, please :)
<terpstra>
it's definitely a bit quirky. it has 34-bit physical addresses from 32-bit virtual.. and 4MB + 4KB page mappings
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<ysionneau>
I would say it would simplify the low level part of the code, you don't need to refill tlb anymore, you just need to update the page table in the OS and give the pointer to the HW
<ysionneau>
but one would need to add support for Sv32 to qemu for instance
<ysionneau>
and also to actually add support for such an mmu to lm32 :)
<ysionneau>
I wonder what those 2 extra physical bits are for
<ysionneau>
hmm I don't see any asid field in the pte
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<ysionneau>
I don't understand how the mmu knows is some pte is "active" or not for current asid/address space
<ysionneau>
-is some+if some
<terpstra>
i intend to use one of the high physical bits to distinguish between cacheable and uncacheable memory
<terpstra>
well, i wasn't planning on backporting Sv32 to the LM32, but rather supporting LM32 on my processor which implements Sv32 :)
<terpstra>
there is a CSR which says the root of the page table
<terpstra>
so, you can tag the loaded PTE entries in the TLB to refer to that particular CSR value
<terpstra>
ie: you don't need to actually blow away all the TLB entries, when someone updates the CSR indicating the root of the page table
<ysionneau>
oh, ok it's like this
<ysionneau>
with asid you could just evict tlb entries when needed, and not just save the life of global ones
<terpstra>
you can still do this
<ysionneau>
oh, or maybe the csr value is like the asid ?
<terpstra>
yes
<terpstra>
when someone writes to the CSR, assign a small tag that means that value
<terpstra>
use that tag on the TLB entries
<ysionneau>
I see, this is totally implementation specific, right? Programmer don't have to know this
<terpstra>
maybe even index the TLB as hash(tag,virtual bits) for a bit better utilization
<terpstra>
exactly
<terpstra>
programmers just fill in the PTE table
<terpstra>
then write to the CSR when they want a context switch
<ysionneau>
yep got it
<ysionneau>
sounds nice!
<terpstra>
how/if the processor optimizes TLB eviction is an implementation detail
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<cr1901_modern>
software refill? I THINK it's self explanatory...