06:56 <sb0> whitequark, the inlining is necessary for the interleave transform

10:28 <cr1901_modern> rj0: I know this is a bit meta, but do you know of an FPGA implementation of an XSVF player?

11:48 <travis-ci> fallen/artiq#243 (gui - 69da1cc : Yann Sionneau): The build passed.

11:48 <travis-ci> Build details : https://travis-ci.org/fallen/artiq/builds/68958211

16:56 <larsc> hm, is this valid verilog 'input foobar = 1'b1;'?

16:57 <larsc> iverilog can't handle it and I can't really find anything on the subject

20:14 <rjo> cr1901_modern: in gateware, no. but iirc openocd is a (x)svf player.

20:15 <rjo> cr1901_modern: but! artiq is much better than a xsvf player. it can do that plus much more. and the relevant parts are in gateware, certainly stand-alone.

20:15 <rjo> its format is not xsvf though, but python. i would imagine xsvf2artiq would not be to hard.

22:08 <ysionneau> it's a bit of a nightmare to debug asyncio stuff when everything is stuck ...

22:08 <ysionneau> because of some exception somewhere or other issue

22:36 <cr1901_modern> I haven't taken much of a look at artiq... probably should change that (it's like super-Migen/MiSoC or something?)