<sb0>
also, green photons, unlike IR, ones can be easily detected with PMTs off taobao instead of 10x more expensive SPADs from annoying suppliers who rarely answer email or phone
<sb0>
China actually has PMT factories with the prices you'd expect, but not avalanche photodiodes afaict
<sb0>
and 10x is giving the western factories too much credit
<sb0>
mh, i have a lot to learn from this paper...
<ysionneau>
sb0: do we want to allow using both ttl_simple and ttl_k7 phys in the same design?
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<sb0>
i don't see why there would be any problem with that
<ysionneau>
at the moment the RTIO module takes the phy_clk as parameter and creates a cd_rio_phy clock domain with it
<ysionneau>
but if we use both ttl_simple and ttl_k7 we have 2 different phy clocks, one at 125 MHz and one at 1 GHz
<sb0>
and "k7" is a bad name for it as it would be compatible with artix and virtex. use e.g. 7series
<ysionneau>
ah yes
<sb0>
if you have to touch anything inside the rtio core you are probably doing it wrong
<sb0>
you can leave the 8x clock free-running from the PLL without dealing with the RTIO reset stuff - that won't hurt
<ysionneau>
ok
<sb0>
and assume that the user provides a rio_phy8x clock somewhere in the design
<sb0>
and that "somewhere" will be rtiocrg, which also needs to take care of any required PLL reset when clocks are switched
<ysionneau>
yep that's what I'm doing now (not pushed yet)
<sb0>
also, the unmultiplied clock is not necessarily 125MHz - it can go up to 146
<sb0>
if the PLL is fine without reset and will relock itself when the new clock is reapplied, don't implement the reset. check the 7-series datasheets to find out...
<ysionneau>
for now I have one BUFGMUX connected to a PLLE2_BASE, maybe I should replace both with just one PLLE2_ADV
<ysionneau>
and use the CLKINSEL
<sb0>
did they document the previously hidden clock switch inside the pll in the 7-series?
<sb0>
and which has lowest jitter? IO->BUFGMUX->PLL or IO->PLL CLKINSEL?
<ysionneau>
they just say that for PLL_ADV and MMCM where you have CLKIN1/CLKIN2/CLKINSEL ports, the PLL is likely to lose lock when switching input clock
<ysionneau>
therefore you need to reset the PLL
<sb0>
well sure it will lose lock
<sb0>
the relevant question is, will it relock correctly without a reset?