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<GitHub157>
[misoc] enjoy-digital pushed 1 new commit to master: http://git.io/vLAOu
<GitHub157>
misoc/master 351e654 Florent Kermarrec: software/bios/sdram: flush dcache and l2 in memtest (otherwise we are partially testing the cache)
<cr1901_modern>
sb0: I need help making a judgment call when you have the chance lol
<cr1901_modern>
In an mibuild file, if a set of pins can both connect to a peripheral AND also be used as a connector, should I place entries for the pins in both _connectors and _io?
<cr1901_modern>
It seems that ConnectionManager can't catch this when servicing plat.requests
<sb0>
you can consider the peripheral an "extension" that gets plugged to the connectors.
<cr1901_modern>
Okay, that's... a really good idea.
<cr1901_modern>
Not sure why I didn't think of that, other than to minimize retyping common peripheral definitions (such as SRAM, shared-SRAM/GPIO-bus).
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<GitHub112>
[migen] enjoy-digital pushed 1 new commit to master: http://git.io/vLxqv
<sb0>
cr1901_modern, can you fix the coding style issues?
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<sb0>
use lowercase, basically
<sb0>
also self.toolchain.xst_opt.replace("SPEED", "AREA") is very fragile
<sb0>
Subsignal("unused", Pins("GPIO:29")), < do you need that?
<sb0>
"SRAM and 5V-tolerant I/O share a parallel bus" this sounds like a bad idea...
<cr1901_modern>
Will fix case issues.
<cr1901_modern>
LM32 won
<cr1901_modern>
't fit unless I do AREA
<sb0>
yes, but better rewrite the whole xst_opt instead of making a fragile replacement
<cr1901_modern>
Oh, alright, can do. Idk what else to change, so I'll just copy the default options to the mibuild file
<cr1901_modern>
sans SPEED
<cr1901_modern>
I need the unused signal so I can Cat() all 30 into a unified GPIO bus. I don't like the design either of shared SRAM and GPIO, but it's what I have to work with.
<sb0>
if a future version of migen uses SPEED elsewhere or stops using the -opt SPEED flag, your code will break
<cr1901_modern>
Ahhh right, that makes sense
<cr1901_modern>
"SRAM and 5V-tolerant I/O share a parallel bus" this sounds like a bad idea... It is. It's the one thing I dislike about this board.
<sb0>
even using -opt speed (in lower case) will break it
<cr1901_modern>
sb0: Posted a corrected patch
<sb0>
cr1901_modern, if you do Cat() and then have signals that go in both directions within it, things will break
<rjo>
sb0, ysionneau: i would run several parallel builds, one with the unittests and the package, and one for each bitstream/bios/runtime. that would imply several conda packages but it speeds up feedback w.r.t. unittests and scales.
<ysionneau>
21:37 < sb0> ysionneau, do you think we can build another KC705 bitstreams on the CI servers, or will that exceed the CPU time limit? < time limit is 45 min IIRC, so far it takes approx 34 min .... that's tight I would say
<ysionneau>
ah no it's 50 min max
<ysionneau>
maybe doable, but dangerously close to the limit
<ysionneau>
rjo: yep that scales better ...
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