lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<rjo> sb0: exactly.
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<GitHub48> [artiq] sbourdeauducq pushed 4 new commits to master: http://git.io/D-7cEw
<GitHub48> artiq/master 27fc19e Sebastien Bourdeauducq: pyon: add doc
<GitHub48> artiq/master 934442b Sebastien Bourdeauducq: pc_rpc: document
<GitHub48> artiq/master ea37274 Sebastien Bourdeauducq: test/pc_rpc: support slow server startups
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<GitHub60> [artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/QoqccQ
<GitHub60> artiq/master 4d0e5db Sebastien Bourdeauducq: doc/manual: split core/controller drivers
<GitHub60> artiq/master 4eda58f Sebastien Bourdeauducq: doc/manual: tutorial -> getting started
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<ysionneau> sb0 : I noticed that If((row_open == 1) and (b == slicer.bank(bus.adr)), does not produce what I expected
<ysionneau> but this does If(Cat(row_open,slicer.bank(bus.adr)) == Cat(1, b),
<ysionneau> is the latter the "best way" of expression the logic "and" ?
<ysionneau> expressing*
<sb0> "and" is not supported
<sb0> use &
<ysionneau> between _Operator it will act as logical and?
<sb0> == returns 1 bit, so logical and boolean "and" are the same
<ysionneau> ah sure
<ysionneau> stupid question :)
<sb0> the problem is Python doesn't support redefining and/or boolean ops
<ysionneau> ok :/
<sb0> but maybe we can throw an error when one does try to use them
<sb0> ysionneau, can you see if adding def __bool__(self): raise NotImplementedError in migen.fhdl.Value does that (and has no ill effects)?
<ysionneau> yep because here it was producing verilog, but just not what I expected
<ysionneau> ok I'll have a look
<sb0> the Python interpreter will try to evaluate the arguments of and/or as bools - we can make that fail loudly
<ysionneau> (use & and | instead of 'and' 'or' fixes my issue)
<ysionneau> sb0: adding the __bool__ prevents the wrong code to produce verilog
<ysionneau> I will keep it here and see if I get weird issues
<sb0> build misoc with it ;)
<ysionneau> let's do that!
<ysionneau> at least it didn't raise any exception, let's see if the bitstream will boot
<ysionneau> bios and app boot :) (cpu is or1k)
<sb0> cool. add a nice message to the exception telling the user to make sure they use & | and send a patch.
<ysionneau> NotImplementedError: For logic operations between expressions: use '&'/'|' instead of 'and'/'or'
<ysionneau> sounds OK?
<sb0> boolean operations
<ysionneau> ok
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<GitHub73> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/fdb_HA
<GitHub73> migen/master 286092b Yann Sionneau: Raise exception when not using correct boolean operators
<GitHub44> [artiq] sbourdeauducq pushed 3 new commits to master: http://git.io/UfF0jA
<GitHub44> artiq/master 1e5b05d Sebastien Bourdeauducq: pdq2: fix commandline arguments
<GitHub44> artiq/master 2946fa5 Sebastien Bourdeauducq: pc_rpc: factor out asyncio server code
<GitHub44> artiq/master d5a3f3e Sebastien Bourdeauducq: doc/manual: driver writing tutorial
<ysionneau> sb0 is I do a sim.run(500) , is it always supposed to finish after 500 clock ticks? What could cause the simulator to get stuck and never finish?
<ysionneau> cause I just changed a few lines (I don't have the exact diff but nothing fancy) and now it does not finish anymore
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<_florent_> hi ysionneau, can you try your simulation with this code? http://git.io/aMr-EA
<ysionneau> what's basically the coding style issue I could avoid?
<ysionneau> hi _florent_ :) and thanks for the patch!
<_florent_> I know that if in a fsm (or a combinatorial block?), if you do:
<_florent_> b.eq(a)
<_florent_> c.eq(b)
<_florent_> it stucks the simulator
<ysionneau> _florent_: indeed your patch fixes my simulation issue!
<_florent_> :)
<ysionneau> many thanks!
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<rjo> research pr, "movie-trailer-style": https://www.youtube.com/watch?v=H08tGjXNHO4
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<ysionneau> very nice!
<mumptai> well done
<mumptai> and they don't personalize it like JAXA did with hayabusa
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