09:03 <key2> joni #m-labs

09:03 <key2> oops :)

09:04 <key2> hi there

09:04 <key2> lekernel still comes here sometimes ?

09:17 <sb0> it's me

10:42 <GitHub46> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/wvQUoA

10:42 <GitHub46> artiq/master 346cca9 Sebastien Bourdeauducq: soc/target: remap RTIO to avoid conflict with spiflash and ddrphy in MiSoC

10:45 <sb0> ysionneau, for the spiflash timing, maybe putting the "If(self.bitbang_en.storage, ..." into a comb statement would help

10:46 <sb0> sorry, I meant a *sync* statement

10:46 <sb0> in slowtan6, two things are particularly slow: 1) CPU buses 2) IOs. so you want to put a maximum of registers between the two.

10:50 <sb0> ysionneau, and since this shifts the output clock by 1 system clock cycle, you should also sample the data 1 system cycle later, e.g. If(i == div//2, dqi.eq(dq.i))

10:56 <ysionneau> ok I'll have a look at putting all this If back into a sync statement

10:58 <ysionneau> is dq.i shifter by one system clock cycle also ?

10:58 <ysionneau> shifted*

10:59 <ysionneau> I can see that it will shift dq.o, dq.oe, cs_n and clk

11:00 <sb0> well of course, if you send the clock pulse one cycle later to the flash, it will send back its data (dq.i) one cycle later

11:01 <ysionneau> yes but if I do If (i == div//2, clk.eq(1) instead of If(i == div//2 - 1, clk.eq(1) (and same for clk.eq(0))

11:01 <ysionneau> then I guess the timing will stay the same?

11:01 <sb0> the data input timing, yes. but this changes the fpga data->flash timing.

11:02 <sb0> since you're then sending the clock at the same time as the current design, but the data (and cs_n) one cycle later.

11:05 <ysionneau> yes then I have to change the value of cs_n and data one system clock cycle earlier also

11:05 <ysionneau> like the clock

11:05 <sb0> yes. you can do it that way too.

11:08 <ysionneau> ok

15:41 <ysionneau> it seems the clock to GDDR5 on the gtx970 is > 7 GHz ?! is that marketing BS?

15:41 <ysionneau> http://www.phoronix.com/scan.php?page=article&item=nvidia_geforce_gtx970&num=3

15:41 <ysionneau> see 3rd screenshot

15:42 <ysionneau> they call is "transfer rate" ... weird

15:43 <GitHub100> [artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/VoBWew

15:43 <GitHub100> artiq/master 9a14081 Sebastien Bourdeauducq: rtio: add pileup count reporting

15:43 <GitHub100> artiq/master 5105b88 Sebastien Bourdeauducq: rtio: raise input overflow exception

15:48 <GitHub190> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/dllGnw

15:48 <GitHub190> artiq/master 97f9c9c Sebastien Bourdeauducq: doc: add precisions on RTIO error handling

15:48 <sb0> ysionneau, no. it's really 7GHz. it's only that you are too much used to slowtan6.

15:49 <sb0> well, 3.5GHz DDR

15:50 <ysionneau> aouch ok

16:14 <sb0> ysionneau, any luck with the timing? maybe the fpga is just too full (in particular because of the mor1kx bloat)... there aren't obvious things in your design that would break timing

19:33 <ysionneau> sb0: I have the same issue, works with blinkie ppro, but does not meet timing with artiq

19:34 <ysionneau> I've put the If in a sync block, and then constraint are met

19:34 <ysionneau> but then it does not boot anymore :p

19:34 <ysionneau> so I must have forgot to deal with some delay