lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<ysionneau>
sb0: hi!
<ysionneau>
how about I start working on a small/simple SDRAM controler?
<ysionneau>
I have a very small understanding of how to control DRAM so I will discover how things work on this topic
<ysionneau>
I will basically have a look at the DRAM chip datasheet I guess
<sb0>
hi
<sb0>
the basic idea is you first open a "row", then you do can read/write data in it (the location in the row is called a column), and finally you close ("precharge") the row
<ysionneau>
ok
<sb0>
there are several "banks" in a sdram chip, and each bank can simultaneously have a row open
<ysionneau>
and the column can contain 8 or 16 bits ?
<sb0>
typically, you'd split a wishbone address as <row address> <bank address> <column address>
<sb0>
yeah, something like that - the exact number is in the sdram datasheet
<ysionneau>
ok
<ysionneau>
so you don't combine several banks during one read, you just read in one bank?
<sb0>
also there are 'bursts': when you read/write one location in the row, you also access the next ones in the following cycles (without sending another read/write command)
<ysionneau>
but if you have several DRAM chips you combine those chips output in one read
<sb0>
yes, read/write commands - like most other commands - are only issued to one bank
<ysionneau>
ok
<sb0>
the typical topology for connecting several DRAM chips is to connect the address/command signals together and have separate data signals for each chip
<ysionneau>
yes ok it's a bit like some spi read/write commands for the flash, where the address can be auto incremented and you just keep reading/writing
<sb0>
it acts like one SDRAM chip with a lot of data pins (with some subtleties about timing when you e.g. use DDR3, which are handled by the PHY)
<ysionneau>
hehe right
<sb0>
DRAM bursts have a fixed length
<ysionneau>
ah
<sb0>
you set it by writing a register and then all accesses are of that length
<ysionneau>
not that flexible, I see
<sb0>
for this small controller though, we will not deal with bursts
<ysionneau>
sure, I guess the idea is to have it the smallest possible?
<ysionneau>
(size of the controler)
<sb0>
yes. when it's connected to SDR SDRAM, disable bursts
<sb0>
and you read 16 bits per WB access (on the PPro)
<sb0>
on the KC705, DDR3 has a fixed burst length of 8, but the clock multiplication in the PHY is also 8, so one SDRAM burst fills exactly one system clock cycle and again you don't have to deal with bursts in the controller
<sb0>
also, you don't bother with the sdram init sequence, the phy infrastructure already does that
<ysionneau>
when you say DDR3 has fixed burst length of 8 it means for one read I get 8*dq_length bits of output?
<sb0>
yes
<ysionneau>
ok
<sb0>
the central part of the controller is a small FSM that takes WB requests on one end, and issues activate/read/write/precharge commands to the sdram
<ysionneau>
yep ok
<sb0>
you need to cut the WB address, and send the row address during activate, and the column address during read/write
<ysionneau>
and use the bank part to control the bank select pins
<sb0>
the bank use dedicated pins, yes
<ysionneau>
BA0/BA1 I think on ppro
<sb0>
yes
<ysionneau>
how do I interface my controller with the "sdram init sequence code"?
<ysionneau>
I need to provide some kind of bitbang interface to the software?
<ysionneau>
or is this already in the PHY part that I won't have to modify that much?
<sb0>
also it's a good optimization to keep the rows open, keep track of which row is open in each bank, and only precharge/activate when you have an actual access to a different row
<ysionneau>
sure
<sb0>
this is handled at the PHY level, you get access to the SDRAM pins all for yourself
<sb0>
through the PHY.
<ysionneau>
ok
<ysionneau>
so basically the abstraction is CPU <-> WB <-> SDRAM Controler <-> PHY <-> actual pins
<sb0>
so the algo is: request coming -> compare row address with current row in the request's bank -> if it doesn't match, precharge/activate -> read/write
<sb0>
you also have to do refresh
<ysionneau>
so I have some counter which counts the time passing and then when it's time I start to refresh all the columns?
<sb0>
you may check the timer only in the FSM idle state (assuming it resets itself and sets a 'refresh needed' flag that the FSM reads and resets), since only the average refresh rate matters
<sb0>
this is much simpler than trying to e.g. abort reads/writes because a refresh is needed
<sb0>
of course, a refresh request takes priority over a wishbone request
<ysionneau>
yep got it
<sb0>
refresh is precharge all -> auto refresh
<ysionneau>
I don't abort, but then before executing next request I do the refresh
<sb0>
yes
<sb0>
note that the precharge all, as its name suggests, closes all rows, so you need to update your tracking. or reopen the previously opened rows just after the refresh.
<sb0>
not reopening and supporting 'no row open' in the tracking is easier, I think
<sb0>
also, DDR3 doesn't like if you reopen rows too fast
<sb0>
(tFAW specification)
<ysionneau>
ok
<ysionneau>
when you say "precharge all" is that a specific command? or do I need to issue 4 precharge commands if for instance I have 4 rows open ?)
<sb0>
precharge all is signalled by asserting A10. the SDRAM then precharges all banks with a single command.
<ysionneau>
funny name "precharge" when it really closes everything :o
<ysionneau>
I would think it would "open" something instead
<sb0>
issuing a precharge all when there are no rows open is OK, so you don't need to deal with that for the refresh
<sb0>
just hardcode precharge all > auto refresh
<ysionneau>
ok
<sb0>
the name comes from "precharging" the column wires to a voltage between 0 and 1, before you connect the capacitive DRAM cells with an activate
<ysionneau>
hum ok :o
<ysionneau>
it doesn't sound impossible to do!
<ysionneau>
thanks a lot for the explanations :)
<sb0>
PCIe Software Defined Radio board with Artix 7 << what's that?
<ysionneau>
some core that _florent_ is writing/has written
<ysionneau>
and that I think he is planning on open sourcing
<ysionneau>
(I mean the PCIe part)
<_florent_>
hi, yes it's a PCIE IP that handles TLPs and provides DMA & Wishbone interfaces
<ysionneau>
hi :)
<_florent_>
ysionneau: btw, if you work with SDRAM, you can use Micron models for simulation, they will be very helpful
<ysionneau>
ah ok, good to know
<ysionneau>
sb0: so I don't need to bother with LASMI or LASMIcon, right?
<ysionneau>
I just do a wishbone slave, that instanciates the sdram phy and sends commands through an FSM
<ysionneau>
no wishbone2lasmi stuff
<ysionneau>
(it's still blury to me the role of each of those components)
<sb0>
no, just WB to DFI
<sb0>
you can look at lasmicon/bankmachine to see how to write the FSM
<ysionneau>
DFI is some well defined and documented PHY interface?
<sb0>
yes, ddr-phy.org
<sb0>
but it's very straightforward, it's basically the SDRAM pins with sometimes a SERDES
<ysionneau>
so I instanciate some dfi.Interface() and I talk to the ram chip through that
<sb0>
yes
<ysionneau>
k
<sb0>
ysionneau, your patches don't apply because copy-paste in roundcube rewraps lines
<sb0>
hmm, maybe it comes from elsewhere...
<sb0>
the lines are only rewrapped (and some spaces inserted) in the message source, not when it is decoded
<GitHub111>
[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/hwS_TA
<GitHub111>
migen/master ff688fb Florent Kermarrec: _Endpoint: allow direct access of payload elements
<GitHub20>
[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/9KUTOw
<GitHub20>
migen/master 07c3327 Florent Kermarrec: use new direct access on endpoints
<GitHub153>
[misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/4CsBUg
<GitHub153>
misoc/master 8e4b898 Florent Kermarrec: use new direct access on endpoints
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<GitHub91>
[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/dWKjFw