<GitHub13>
artiq/master 5d8c53a Sebastien Bourdeauducq: soc/runtime/exceptions: do not crash when exception is raised with no handler
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<sb0>
rjo, how do we clock the ppro from the same PLL that drives the DDS system?
<sb0>
and do we bother at all, or do we consider the ppro an inferior platform where FUD setup/violations are acceptable?
<sb0>
if ISE clock management works correctly (which rarely happens with s6 tbh), it should be possible to have a smart clock switching where the FPGA automatically switches to the external clock when it is applied and locks a PLL/DCM. at least the FPGA arch supports that...
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<GitHub86>
[artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/keWiuw
<GitHub86>
artiq/master 2f58cf6 Sebastien Bourdeauducq: examples: add main function