lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0>
ysionneau, because the CPU, not the gateware (wishbone to CSR bridge) does the width conversion
<sb0>
maybe we could change that, it shouldn't use a lot of resources and would make the csr a bit faster (for e.g. rtio) and easier to use in the bios
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<sb0>
sj_mackenzie, are you going to dsl tonight?
<sj_mackenzie>
sb0: yes I'll be there about 8pm. drinks?
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<sb0>
yes!
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<sj_mackenzie>
sb0: see you - btw I've thought a bit about that project. Would prefer to print the nand2tetris cpu aka the Hack CPU (http://nand2tetris.org/05.php). This feels more approachable for me :
<sj_mackenzie>
)
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<sb0>
sj_mackenzie, how do you synthesize that to hw?
<sb0>
and chances are it's larger than the 6502 =]
<GitHub19>
artiq/master 2449348 Sebastien Bourdeauducq: devices/runtime: allow 1ms for all initial DDS programming
<GitHub19>
artiq/master 7d48ef2 Sebastien Bourdeauducq: soc/runtime: fix RTIO sequence error detection on FUD
<sb0>
rjo_, btw we can do bd.pulse(100*MHz, 20*ns); bd.pulse(200*MHz, 30*ns) if the channel was off for enough time before (and the current driver does this)
<sb0>
the first FUD will be soft-timed during the off period, then the sw prepares the registers for 200MHz, and sends a hard-timed FUD 20ns after the rf switch is turned on
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<GitHub11>
[artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/it_eIQ
<GitHub11>
artiq/master b6ac4bd Sebastien Bourdeauducq: transforms/tools: support NameConstant
<GitHub11>
artiq/master 754a06c Sebastien Bourdeauducq: transforms/fold_constants: support BoolOp
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<ysionneau>
23:24 < rjo> ysionneau: did you also physically move to .hk? < nop, still in Paris :)
<GitHub76>
[artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/ly4LbA
<GitHub76>
artiq/master d22c306 Sebastien Bourdeauducq: rtio: add timestamp function
<ysionneau>
funny to see the looong first clock tick, which I think must come from the fact that the for loop isn't in the CPU Instruction Cache yet
<ysionneau>
:)
<sb0>
good :)
<sb0>
and yeah, the sdram access from the CPU is suboptimal
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<mwalle>
ysionneau: what board is that? artiq stuff?
<mwalle>
sb0: ysionneau: and why not use a small 8-bit based spi controller?
<ysionneau>
I'm using the papilio pro board
<mwalle>
ysionneau: for what? misoc stuff?
<ysionneau>
for artiq yes
<ysionneau>
no need to redesign the board just to write a few configuration data in the flash
<mwalle>
nah, i've meant as a core in the fpga
<mwalle>
byte access to some registers, which results in serial output (MOSI/SCK) and serial input (MISO)
<ysionneau>
that would be nice also indeed
<ysionneau>
but as I understood there is no need for that here since slow access through bit banging is enough here
<ysionneau>
the erase/write will be very rare (or not much data)
<ysionneau>
reads keep being generated by hardware though
<mwalle>
is this the configuration flash?
<ysionneau>
I'm just adding a simple bit banging access in order to provide slow access to the flash for whatever command is possible (erase/write, OTP etc)
<ysionneau>
yes it's the flash used for bitstream+bios+app
<_florent_>
hi
<ysionneau>
hi _florent_ :)
<ysionneau>
_florent_: thanks for your answer to my lat email!
<ysionneau>
last*
<_florent_>
ysionneau, I've done something similar last week
<mwalle>
mh, and the fpga reads bios and app in hardware?