lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<rjo> sb0: yep. i have been playing with the fully integrated cathode drivers. feedback and stability are a bit problematic but if i have enough time, they have been my favourite. i believe i sent a few links.
sj_mackenzie has joined #m-labs
<sb0> those are higher voltage than the ones you sent, though
<sb0> and discrete
<sb0> sounds they'd do those 50MHz/50V/20pF.
kmehall_ has joined #m-labs
siruf_ has joined #m-labs
kmehall has quit [Ping timeout: 264 seconds]
siruf has quit [Ping timeout: 264 seconds]
ohama has quit [Read error: Connection reset by peer]
ohama has joined #m-labs
siruf_ is now known as siruf
<rjo> sb0: yes. a bit higher voltage. but they are not as nicely integrated. maybe with proper dirving, working point, linearization, feedback etc they'd work.
<rjo> sb0: do you have the pnp in class a with common collector in mind for those? or push-pull?
<rjo> weird. they are not EOL yet even though nobody does CRTs anymore. the CRT drivers from TI are all EOL.
<rjo> and why are we back to semiconductors now? ;)
<sb0> they list "wideband amplifier" as alternative application
<sb0> what I have in mind is a common collector class B push-pull, diodes to reduce the dead-zone and limit the required slew rate when switching to one transistor to the other, a class A voltage preamplifier, and a feedback loop with op-amp
<sb0> perhaps all DC coupled
<sb0> the problem with direct class A output is that your bandwidth is limited by the RC circuit formed by the load resistor and the electrode's capacitance, which requires the resistor to be small, and thus dissipate a lot of power when the required amplitude is large
<mithro> afternoon people
<mithro> does migen / misoc have any "ethernet" support at all?
<sb0> yes
<rjo> mithro: howdy. how do you generate that 1GB ISE thingy?
<mithro> rjo: you mean the cutback ISE that shenki created which only works for compiling the HDMI2USB firmware?
<rjo> maybe. you mentioned that a while ago. do you have a link?
<mithro> not yet
<rjo> mithro: i looked at your docker recipe for ise. but i never really understood why people want docker for development tools. i do however understand why docker is cool for server farms.
<rjo> mithro: how do you cut it down? i was considering running it under strace and deleting all files that are never open()ed...
<mithro> rjo: pretty much what we did :)
<rjo> mithro: ha. good ;)
<rjo> sb0: i never developed a comfortable level of intuition for these non-trivial transistor circuits. wouldn't the feedback phase lag through such a large circuit be a real problem here?
<sb0> hmm, with all the parasitic capacitances, maybe
<rjo> mithro: would be awesome if xilinx would sponsor a open source build bot. e.g. through travis-ci.
<rjo> sb0: otoh, if the feedback was slow and based just on phase and amplitude through power/phase detectors or the like, that might be sufficient.
<sb0> i'd say the simple dc-coupled feedback might be worth a try.
<rjo> with integrator sample-and-hold if that electrode is off... bah. complicated.
<sb0> you can use one of those power transistors for the class A preamp, and a small load resistor, to reduce the influence of parasitic caps there
<sb0> the diode stuff doesn't add to the capacitance
<sb0> if the capacitance of the electrodes causes problems with the feedback, it helps to put a small resistance in series after the feedback
<rjo> yep. i did that with the opamps as well.
<rjo> the transistors look beefy. good find!
<sb0> for the diodes, here's what I mean: http://www.ecircuitcenter.com/Circuits/pushpull/pushpull.htm
<sb0> "diode bias"
<rjo> sb0: i think with a few small modifications pyon could be made a superset of json. and then one would only need to restrict the parts that are exposed outside artiq to json.
<sb0> when there's op-amp feedback, you can remove them, however the op-amp will have to speed through the dead zone which may cause problems at high frequencies
mumptai has joined #m-labs
<sb0> yes, the syntaxes are very similar. it's mostly about using ' to delimit strings instead of "
<sb0> which can be changed
<rjo> sb0: re diodes and feedback: ack.
<rjo> sb0: and null vs None. and potentially the newline rules.
<sb0> also True vs. true
<sb0> we can do "true = True" in the pyon namespace dictionary
<sb0> or ditch the eval() hack and use a grammar file, which can be useful to people reimplementing the full pyon in another language
FabM has joined #m-labs
kmehall_ is now known as kmehall
mumptai has quit [Quit: Verlassend]
sj_mackenzie has quit [Remote host closed the connection]
sj_mackenzie has joined #m-labs
_florent_ has joined #m-labs
<GitHub170> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/l1DNyQ
<GitHub170> artiq/master 6e21946 Sebastien Bourdeauducq: py2llvm: support operations between fractions and floats
sj_mackenzie has quit [Remote host closed the connection]
<GitHub107> [misoc] sbourdeauducq pushed 4 new commits to master: http://git.io/8h1LAw
<GitHub107> misoc/master f33b285 Yann Sionneau: Minicon: small SDRAM controller
<GitHub107> misoc/master cf92821 Yann Sionneau: Refactor directory hierarchy of sdram phys and controllers
<GitHub107> misoc/master 8418cca Sebastien Bourdeauducq: minicon: remove unused signals and fix indent
<ysionneau> ah I was using the wrong phase?
<ysionneau> maybe that fixes the M1/DDR case
<sb0> yes, please try that
<ysionneau> it's MUCH better now!
<ysionneau> still 794768/1048576 words incorrect in memtest
<ysionneau> so not perfect yet
<ysionneau> but in the BIOS I can write and read back the same value
<ysionneau> which I was never able to do before
sb0 has quit [Quit: Leaving]
sb0 has joined #m-labs
<ysionneau> so 75% of the memtest is still failing ...
<GitHub153> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/FjSqHg
<GitHub153> artiq/master 41ecf09 Sebastien Bourdeauducq: doc/manual/installing: add missing cd
<ysionneau> in the failing cases, the least significant byte is always correct, like array[0] = 54cc165f != 3c6ef35f
<ysionneau> (I'm printing "array[%d] = %08x != %08x", i, array[i], prv)
<ysionneau> memtest is mostly KO (75%) but there are 'big' rows of successful read backs, in those rows you get very few isolated errors, and those errors are almost always exactly separated by 54 accesses
<ysionneau> in the 'KO' rows you also get some isolated successful read backs, some of them are separated by 54 KO ...
<ysionneau> and when repeating the memtest I get the same exact results (compared from array[0] to array[2558])
<ysionneau> maybe that's some corner case due to the refresh ...
<GitHub137> [misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/A4VSJQ
<GitHub137> misoc/master bab6bb7 Sebastien Bourdeauducq: gensoc: fix align
<GitHub137> misoc/master edb1622 Yann Sionneau: spiflash: BB write support
sj_mackenzie has joined #m-labs
<ysionneau> I tried to reduce tREFI, each time I reduce it, the failure % is going up
<ysionneau> it might be that I'm violating tRAS if right after an Activate, I get a refresh_req which will then do a prechargeall thus violating the Activate-to-precharge time
<ysionneau> tRAS should be 40 ns, for now after an ACT we wait 15 ns (tRCD)
<ysionneau> let's try 40 ns ...
<ysionneau> wrong track, does not improve anything in the fail rate
zumbi has quit [Ping timeout: 255 seconds]
_florent_ has quit [Ping timeout: 240 seconds]
_florent_ has joined #m-labs
_florent_ has quit [Quit: Leaving]
zumbi has joined #m-labs
sj_mackenzie has quit [Remote host closed the connection]
_whitelogger has joined #m-labs
mumptai has joined #m-labs
mumptai has quit [Quit: Verlassend]