lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub193>
[artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/Tylefw
<GitHub193>
artiq/master fba72cc Sebastien Bourdeauducq: transforms/remove_inter_assign: support names and dependencies
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<rjo_>
ysionneau, sb0: since the __bool__ exception one of the unittest fails. i assume that part of the test is now invalid.
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<sb0>
rjo, hmm looking at it, it seems the test was incorrect in the first place. you are doing self.assertEqual(si, self.s[i]) between fhdl.structure._Slices, which returns an _Operator, which you then test as boolean. it used to return True (bool() of a user object is true), now the __bool__ exception catches the error...
<sb0>
let me fix it
<GitHub171>
[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/0Iv1hQ
<GitHub121>
[artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/-G00MA
<GitHub121>
artiq/master f54a2f9 Sebastien Bourdeauducq: remove kernel_attr (inline transform is now smart enough to autodetect)
<rjo_>
sb0: what do you think about a "CSRConstant" that does not use up resources in the csr banks/busses but would still be extracted and exposed like a read-only csr during the csr map generation?
<rjo_>
sb0: would also be nice for csr map versioning, like (get_identifier_revision() == get_identifier_csrmap_revision())
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<sb0_>
rjo, should this be a fake csr, or equivalent to the current CSRStatus with a constant assign?
<sb0_>
rjo, I'm actually thinking of letting modules define arbitrary software-exposed constants, which would be also useful for flags/bitmasks (instead of the current manual coding in hw/flags.h)
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<ysionneau>
sb0_: once I have an Array() for openrow, in the row_closeall case, can I do something "like" openrow[*][-1].eq(0) ?
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<sb0_>
yes
<sb0_>
but your current code is ok
<sb0_>
(migen would actually lower Array to what you have written)
<ysionneau>
ok
<ysionneau>
cause I just put something like this instead of iterating through the banks :
<sb0_>
also, you need closeall, which will be a bit messy to implement with array. I suggest keep the current code.
<ysionneau>
sb0_: about dfi address driving, I can use some address_selector Signal() that can take constant values like COLUMN or ROW or A10_ENABLED ?
<ysionneau>
with those 3 being just python constant ints in uppercase
<sb0_>
yes
<sb0_>
lasmicon does that, no?
<ysionneau>
something like that phase.address.eq(Array(cmd.a for cmd in commands)[sel]),
<sb0_>
Array([col, row, 2**10])[sel]
<sb0_>
maybe 2**10 first
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<GitHub115>
[artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/5Jqu1g
<GitHub115>
artiq/master 9b93b0c Sebastien Bourdeauducq: unparse: string-based API
<ysionneau>
sb0 : about row_close being useless, you mean that anyway just after that we will reopen a row so it's useless to set the "active" bit to 0 and then set it to 1 again right after?
<ysionneau>
yes ok I see, we never just do a precharge just like that whithout an activate after
<ysionneau>
the "active" bit then is just cleared upon prechargeall
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