lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> yay, 125MHz rtio is working stable on the ppro now
<sb0> also all fifos, including outputs, are block-rammable
<GitHub10> [artiq] sbourdeauducq pushed 5 new commits to master: http://git.io/h3JmsA
<GitHub10> artiq/master 9aafe89 Sebastien Bourdeauducq: rtio: use Record
<GitHub10> artiq/master 39c4b54 Sebastien Bourdeauducq: targets/ARTIQMiniSoC: 125MHz RTIO clocking
<GitHub10> artiq/master c78c5a2 Sebastien Bourdeauducq: rtio: fix guard cycle computation
<sb0> rjo, can we use PMTx or XTRIG to send the dds clock to the fpga?
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<GitHub90> [artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/8KDa-Q
<GitHub90> artiq/master 1f64419 Sebastien Bourdeauducq: more TTL channels and larger input FIFOs on Papilio Pro
<GitHub90> artiq/master e5286c5 Sebastien Bourdeauducq: rtio: fix input FIFO depth config
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<GitHub62> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/Pk_dOA
<GitHub62> migen/master ae770c0 Sebastien Bourdeauducq: bank: support direct mapping of CSRs on Wishbone
<GitHub160> [misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/ukvMew
<GitHub160> misoc/master 8ae3a00 Sebastien Bourdeauducq: gensoc: simplify WB address decoding
<GitHub160> misoc/master aac34f0 Sebastien Bourdeauducq: gensoc: support user-defined CSR regions
<GitHub34> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/PsmNNQ
<GitHub34> artiq/master 7166ca8 Sebastien Bourdeauducq: targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%)
<sb0> it's interesting that or1k-gcc generates slightly faster code for "if(!rtio_o_writable_read()) {while(!rtio_o_writable_read()); }" than for "while(!rtio_o_writable_read());" alone
<sb0> also, for some reason "while(!rtio_o_writable_read());" takes 50 CPU cycles when the loop is not entered
<sb0> rtio_o_writable_read() just reads a 32-bit word from a static addr