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<
TheLinuxBug >
Any of your guys going to go to ESC in Boston, MA coming up?
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<
wens >
jernej_: it's not working
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<
kloczek >
someone have idea how to setup fixed mac address on pine64 eth0 NIC? (kernel 4.11 rc5)
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<
montjoie >
set it in DT ?
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<
plaes >
or udev rule
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<
plaes >
it all depends on which level...
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<
KotCzarny >
kernel cmdline param?
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<
kloczek >
plaes: kernel 4.11 rc5
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<
plaes >
is it possible? :)
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<
kloczek >
KotCzarny: of courrse but which one? :)
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<
kloczek >
problem is that in this case it is possible identify such NIC by physical path
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<
MoeIcenowy >
wens, mripard: some work from megous have shown that the factors in PLL_CPUX has some restrictions
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<
MoeIcenowy >
and the rule that "M shouldn't be used, P should only be used when <288MHz" can be proven by stock clk-sun8iw7_tbl.c
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<
wens >
then send a patch to drop it to an NK clock?
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<
MoeIcenowy >
I remembered megous did a local hack that set the maximums of the factors to 1
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<
MoeIcenowy >
and a U-Boot fix that removed the usage of M
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<
MoeIcenowy >
These fixes are verified in Armbian
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<
MoeIcenowy >
oh megous didn't add a Signed-off-by at his patch
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<
MoeIcenowy >
should I keep the patch's author to him?
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<
MoeIcenowy >
oh the P fix is weird...
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<
MoeIcenowy >
he hardcoded 288MHz value in ccu_nkmp.c
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<
MoeIcenowy >
but I think we can just restrict the maximum of P to 1
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<
wens >
you can just drop it from the clock, but force it to 1 at probe time
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<
wens >
i'm doing this for the a80
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<
MoeIcenowy >
ok ;-)
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<
MoeIcenowy >
but they're dividers
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<
MoeIcenowy >
if we force it to 1, it may lead to direct system hang
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<
MoeIcenowy >
so a up to date u-boot will be needed for it to properly work
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<
MoeIcenowy >
wens: how to deal with this?
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<
wens >
fix up the multipliers
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<
MoeIcenowy >
re-calculate the frequency when setting the divider?
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<
wens >
there is always the possibility that the user is not using mainline u-boot, or even an up to date one
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<
wens >
MoeIcenowy: something like that, yes
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<
wens >
or you could just force it to a safe frequency
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<
wens >
that would work
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<
MoeIcenowy >
P.S. the staged setting can be omitted if the clock is proper
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<
MoeIcenowy >
and as megous said, staged setting will sometimes still fail
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<
MoeIcenowy >
let me first send out the U-Boot patch
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<
MoeIcenowy >
wens: it's possible to get the system to hang when setting the failsafe frequency...
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<
MoeIcenowy >
we should do the right thing ASAP ;-)
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<
MoeIcenowy >
wens: the process that forces the clock will directly hang the system...
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<
MoeIcenowy >
the best result here is: patch u-boot, keep the staged factors applying patch and add factor maximum
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<
victhor >
I'm having problems trying to enable UART1 on PD10 and PD11 on a A33, mainline kernel 4.9.15. I get a message on my kernel log saying the UART is enabled but it doesn't work. I have not made any changes to u-boot, however, only to the dts file.
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<
victhor >
I have not removed the PD10 and PD11 from the lcd controller definition, I overlooked that...
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<
victhor >
hmm, still not working
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<
MoeIcenowy >
could you upload the final dtb file somewhere?
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<
victhor >
sure, just a moment...
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<
victhor >
that should be it
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<
MoeIcenowy >
q8 tablet...
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<
victhor >
yes, I have a board from a broken system and wanted to enable UART1 on the LCD pins so I wouldn't have to have the LCD connected all the time
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<
MoeIcenowy >
seems no problem...
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<
victhor >
I can export the GPIOs for PD10 and PD11, which is strange, shouldn't they be used by the driver, and return an error when exported?
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