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<KotCzarny>
hmm
<KotCzarny>
that 850C looks like typo from 85C
<plaes>
yup
<KotCzarny>
which could mean a10/a20 shouldnt be pushed over 85C
<SMDwrk>
plaes: thanks, I've seen this, but it doesn't answer my question( Memory map and etc is ok, but there is nothing about stock firmware for it or anything similar
<SMDwrk>
I'll try to download sdk and search there for some blobs though
<plaes>
yeah.. we can't really distribute those blobs :(
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<SMDwrk>
The idea is to make powerbutton work(again, if anyone has it working, please let me know) with help of existing firmware
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<wens>
SMDwrk: nope
<SMDwrk>
wens: sorry, what that "nope" refers to?
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<plaes>
Kernel_Panic: do you plan submitting patches?
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<wens>
SMDwrk: no sources for ar100 blob
<SMDwrk>
wens: ok, but is there blob itself in i.e. sdk or maybe it's in rom?
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<plaes>
SMDwrk: found one via google
<SMDwrk>
plaes: I've found some blobs and arisk driver in the sdk, need to test it this evening
<SMDwrk>
megi: thanks, next stop is to load original ar100 blob into sram and test powerbutton
<megi>
but you don't need this to get access to the reset button, it's just connected to GPIO and configured in dts file, you just need to configure it somehow
<megi>
if you're on the mainline kernel
<megi>
you can access whatever ar100 has access to from the main cpus too
<megi>
so creating some userland app watching the appropriate gpio and reacting to it (reset, shutdown, whatever) should work too
<SMDwrk>
megi: I'm talking not about reset but about power button, as far as I understand if I press powerbutton soc has to go to sleep(?) mode and if I press it again it should boot or something like that. Correct me, plz, if I'm wrong
<megi>
I'm not sure what it does. On my opi pc there's just a single button and it's connected to gpio. So it can do whatever you program it to do.
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<megi>
Sleep might be tricky, though. :) Because then, you'd really need to use ar100, because the main cpu will be down.
<SMDwrk>
megi: exactly! that's what I'm talking about
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<megi>
I tried to disassemble the ar100 blob for h3 some time ago, and the only disassembler i could find for openrisc missed half of the instructions. It was not readable at all.
<megi>
and IDA doesn't have openrisc support either
<SMDwrk>
megi: disassembling 250kb blob seems hardly impossible to me
<megi>
if you find working disassembler
<megi>
with the one in the toolchain you just get 30% symbolic instructions mixed with 70% raw bitcode
<megi>
tough to interpret that
<SMDwrk>
megi: that's weird
<megi>
please let me know if you find some working disassembler, I'm also interested in this, because I'm working on making the power management work on orange pi pc
<SMDwrk>
megi: Thanks, sure!
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<ssvb_>
SMD1: what are you trying to find in this binary?
<ssvb_>
SMD1: yes, of course disassembling it always worked fine, but are you looking for some specific information or something?
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<megi>
SMD1: thanks for the disassembly
<megi>
SMD1: there's a lot of strings (and possibly other data) in the binary (visible clearly if you do the 4byte reverse on all DWORDs), so I think that's what's behind the unknown parts
<ssvb_>
SMD1: btw, you are disassembling it slightly wrong
<ssvb_>
megi: oh, you are also interested in the OpenRISC disassembly?
<megi>
ssvb_: yes
<ssvb_>
looking for something there?
<megi>
I was looking in there, for ways to communicate over r_twi with SY8106A on the opi pc board, but figured it out without it
<ssvb_>
yes, SY8106A is already supported in U-Boot
<megi>
I know, I also wrote support for the linux kernel
<megi>
now I'm just curious what other thing is there, and if it would be possible to support some deeper idle states
<megi>
in the mainline
<ssvb_>
there must be some code, which puts DRAM into the self-refresh mode and then brings it back
<ssvb_>
but I believe I have seen some sources for this somewhere in the SDK
<apritzel>
does the arisc code for the OrangePi block access to the R_ peripherals somehow? Specifically the RSB? Or could you still access it directly from U-Boot, for instance?
<megi>
tha ar100 is held in reset by default
<megi>
on mainline
<megi>
so it doesn't block anything
<apritzel>
I meant if there is something running on it
<megi>
everything that's acessible from ar100 also works from the main cpu, afaik
<apritzel>
right, my impression, too
<megi>
so I'd guess that no
<apritzel>
I just couldn't access the RSB from U-Boot on the Pine64
<ssvb_>
apritzel: yes, I was going to take care of the A64 PMIC support eventually
<apritzel>
and I was wondering if that's just me being stupid or some hardware restriction
<ssvb_>
maybe some magic bit needs to be set somewhere
<apritzel>
my understanding is that the R_ peripherals _can_ be made secure-only and thus blocked from the ARM cores running non-secure
<apritzel>
ssvb_: A64 PMIC support> great! I was hoping that you would take a look
<apritzel>
I removed the need for the arisc code from the ATF
<apritzel>
so secondary core bringup is now done directly without calling into the arisc
<apritzel>
so the OpenRISC is free for people to play with... \o/
<megi>
:)
<apritzel>
including some proper PMIC controller code
<ssvb_>
did you use the disabled bits of code from the Allwinner's SDK for the secondary cores bring up?
<apritzel>
yes, that's what I enabled again ;-)
<apritzel>
so far PSCI CPU_ON works, all four cores are on
<ssvb_>
that was very nice of them to keep it for reference :-)
<apritzel>
indeed ;-)
<apritzel>
RESET and POWEROFF are not implemented (yet)
<apritzel>
POWEROFF requires PMIC access (I guess)
<apritzel>
could RESET be done with some watchdog or the like?
<ssvb_>
yes, reset is usually implemented using a watchdog
<ssvb_>
on all the other Allwinner SoCs
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<apritzel>
great, I was hoping for that
<ssvb_>
megi: as for the H3 arisc code disassembly log, a part of it is loaded into the DRAM because the SRAM A2 is only 32K
<ssvb_>
megi: so don't be surprised about the addresses which start from 0x4308XXXX
<megi>
hmm, ok :)
<ssvb_>
but I still suggest you to scan the SDK sources for the self refresh code, that's what is needed for suspend to ram support
<megi>
btw, sunxi website is not working atm
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<ssvb_>
the arisc firmware also seems to be responsible for some audio support (maybe some low power music playback support when the ARM cores are powered down?), but I'm not sure if it is very interesting at this moment
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<ssvb_>
the blob seems to be unreasonably large for what it is supposed to do
<megi>
yes, it has some uart/debug interface too
<megi>
that may be part of the bloat
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