<swkhan>
azonenberg_work: that sounds good. i'm not sure were i can pick them up without alerting other group mates to what i'm doing
<swkhan>
i should specify one thing. the furnace usually grows some iii-v semiconductor nanowires
<swkhan>
and the surrounding quartz will need to be cleaned. do you mind if i keep some of the pieces of silicon? like take a wafer and cut it into a bunch of pieces and try to grow the thermal oxide on some for you + send them to you and then keep some for myself so it looks like i'm doing something with it too?
<azonenberg>
Just got back from a meeting of the Capital District Microscopy and Microanalysis Society  (http://cdmms.org/)
<azonenberg>
I highly recommend similar groups if you can find any locally
<azonenberg>
the lecture today was on microscopy of semiconductors, by a FA engineer at IBM
<kristianpaul>
cdmms know about your current work about homecmos?
<azonenberg>
kristianpaul: A few of the members do
<azonenberg>
i havent presented or anything
<azonenberg>
But i've asked around for advice on sample prep etc
<azonenberg>
I actually just joined today
<azonenberg>
I know several of the members and wnated to join before but coudlnt make the last meeting
<azonenberg>
its usually every couple of months (3-5 times a year)
<azonenberg>
They seem to be mostly focused on the various forms of electron microscopy but there is definitely interest in light microscopy as well as general sample prep techniques etc
<gkwhc>
Hi, I'm new to semiconductor design & fabrication. I'd like to know if it will be hard to design/fabricate a simple logic/counter chip that runs on 0.005uA? Would this be a design problem or a fabrication problem, or both?
<azonenberg>
gkwhc: Depends on what fab you're using, to start
<azonenberg>
This channel is a little less about chip design (for now, at least) and more on building a working fab from scratch
<azonenberg>
if you're using a "real" process in a "proper" lab it's a lot more doable
<azonenberg>
5 nA is low, but for only a few gates on a low-leakage process tech it should be possible
<azonenberg>
On 20 micron living room CMOS, i'd say most likely not
<azonenberg>
I'm focusing on MEMS right now but in a year or so i'll probably have made a working chip with a couple of gates on it (most likely a 74HC04 or similar in a 14-ball CSP BGA)
<azonenberg>
as in power, ground, six in, six out
<azonenberg>
In terms of "a simple logic chip"
<azonenberg>
what are you starting from
<azonenberg>
pre-existing cell library, just arranging gates?
<azonenberg>
drawing each transistor yourself?
<gkwhc>
azonenberg: I might be drawing each transistor for a greater learning curve
<gkwhc>
i know a university that has proper equipments, but I am not sure if the 5nA is achieved through proper design or proper fabrication?
<azonenberg>
gkwhc: Both
<azonenberg>
Do they have a course in vlsi design?
<azonenberg>
And/or fab techniques?
<gkwhc>
no, unfortunately
<azonenberg>
But you say they have fab equipment?
<gkwhc>
well, I am an undergraduate student. most people who operate the equipments are graduate students who have had proper training/knowledge of the manufacturing process
<azonenberg>
Oh, i see
<azonenberg>
Well, you can always jump ahead in the theory
<azonenberg>
start learning layout yourself
<azonenberg>
there are a bunch of free tools for design, i linked to several on the project wiki
<gkwhc>
yes! i downloaded several of them
<azonenberg>
If you hang out here we'll gladly discuss layout issues etc
<gkwhc>
can you suggest any getting-started ebooks/guides?
<azonenberg>
I'm a bit busy right now as i have homework due tomorrow morning
<azonenberg>
and hmm
<gkwhc>
ah i see
<azonenberg>
wikibooks has a nice one on microfab but thats mostly fab processes
<azonenberg>
and less on the design
<gkwhc>
mhm
<azonenberg>
It depends also on what you want
<azonenberg>
For example, B0101 is interested in Josephson junctions
<azonenberg>
I'm doing MEMS but want to try CMOS at some point
<azonenberg>
You want to do digital logic but are you more interested in MOS, bipolar, or not sure yet?
<gkwhc>
I am not quite sure yet - the only constraint is very low current consumption :)
<azonenberg>
What's your use case?
<gkwhc>
Learning-by-doing a watch/clock logic, like how the industry does it.
<gkwhc>
I mean, using a MCU is overkill
<azonenberg>
Ok
<azonenberg>
Well, there are a couple of things to do
<azonenberg>
The first is to prototype your design in an FPGA or (better) a CPLD, using as few gates as possible
<azonenberg>
At some point in the future you can then turn that into a netlist suitable for fab
<gkwhc>
mhm
<gkwhc>
I see
<gkwhc>
and then I will need to use the EDA software like Alliance or Magic to create the layout?
<azonenberg>
Yes
<gkwhc>
thanks :)
<azonenberg>
And then as for fab, well, there are a couple routes to go
<gkwhc>
mhm
<azonenberg>
Send it out to a commercial shop like MOSIS (expensive, doesn't teach you much, but will give you the best chance of working)
<azonenberg>
Build it yourself in a proper lab (less expensive, you learn a lot, but you might screw it up)
<azonenberg>
and hack it up in a home lab
<azonenberg>
Cheaper to operate (though equipment costs may be high as you get started), extremely educational
<gkwhc>
I was quite surprised to hear that  ahome lab is possible!
<azonenberg>
I havent uploaded all of them yet unfortunately
<azonenberg>
and it is here too
<azonenberg>
where you at?
<gkwhc>
Virginia Tech :)
<azonenberg>
Ah
<azonenberg>
RPI here
<gkwhc>
cool!
<azonenberg>
i'm off to finish two more hw problems before class tomorrrow
<azonenberg>
ttyl
<gkwhc>
bye! and thanks again!
<azonenberg>
AFKs
<azonenberg_work>
Well... looks like I may not be getting much lab work done for a few days - homework to do, then busy all weekend
<azonenberg_work>
But I want to do some KOH tests soon
<azonenberg_work>
hopefully sunday evening or monday
<azonenberg_work>
Or, if i'm lucky, tonight
<bart416>
azonenberg_work, we had a funny discussion today with some people at university
<bart416>
Writing a website in VHDL :P
<bart416>
Obviously integrated the web server into the fpga with only an external IC for the hardware layer of the network
<azonenberg_work>
bart416: lol
<azonenberg_work>
Would that be done with a softcore cpu (easy) or just raw tcp/ip/ethernet?
<azonenberg_work>
Would be fun to say the least
<azonenberg_work>
the lowest i've gotten so far was a webserver in x86-64 asm (no libc, just linux syscalls)
<azonenberg_work>
but i used the linux tcp/ip stack
<lekernel>
people did that already
<lekernel>
there's a youtube video of it
<lekernel>
it's a pretty stupid thing to do however
<azonenberg_work>
Yeah
<azonenberg_work>
More of a stunt than useful
<bart416>
raw tcp/ip ofc
<bart416>
No OS
<azonenberg_work>
lol yeah
<bart416>
You have the hardware layer provided by the IC
<bart416>
But that's it
<bart416>
lekernel, it's still an interesting exercise
<bart416>
Especially if you would write a cross compiler
<bart416>
Say convert PHP to VHDL and then send it to whatever FPGA that you have
<azonenberg_work>
Oh, lol
<azonenberg_work>
server side scripting, not just static content?
<azonenberg_work>
better yet, no cross compiler
<azonenberg_work>
actually write HDL for the script :P
<bart416>
lol
<bart416>
That'd be hard
<bart416>
But if you'd convert PHP it would actually be useful
<azonenberg_work>
reg[511:0] hdrs;
<bart416>
meh :P
<azonenberg_work>
initial begin \ hdrs = "HTTP/1.1 200 OK\r\nX-Server: XC3S200A\r\n\r\n";
<azonenberg_work>
lol
<bart416>
The latest in Cloud-HDL-Computing!
<azonenberg_work>
lol
<bart416>
We could start a new cloud hype with this lol
<azonenberg_work>
One thing's for sure, it would be fast
<azonenberg_work>
imagine having fifty webserver modules muxed into a giant output FIFO and an ethernet PHY
<bart416>
yeah, if you think about it, for a system that doesn't change often it'd actually be pretty effective
<azonenberg_work>
store static html in block ram
<azonenberg_work>
you could probably push Gbps of data without even trying too hard
<azonenberg_work>
the NIC would be the bottleneck
<azonenberg_work>
have preformed IP packets that you just patch up sequence numbers etc :p
<bart416>
Meh, 10 Gbps should be enough :P
<azonenberg_work>
lol
<azonenberg_work>
XC6SLX75T plus GBIC slot?
<azonenberg_work>
s/GBIC/SFP
<bart416>
lol
<azonenberg_work>
Or ditch the SFP and just have a raw fiber connector
<bart416>
What we're actually considering doing is building a complete processor on transistor level (16 bit) without any help from software
<azonenberg_work>
who's "we"
<bart416>
EE students
<azonenberg_work>
and you want to do it by hand, like the 4004 was?
<azonenberg_work>
or using cad but no synthesis?
<bart416>
by hand
<azonenberg_work>
i.e draw out cells, then place and route by hand?
<bart416>
No software
<azonenberg_work>
THAT is just crazy lol
<bart416>
No PCBs though
<azonenberg_work>
i could understand doing it without synthesis
<bart416>
Just wiring
<azonenberg_work>
Oh
<azonenberg_work>
i thought you meant vlsi lol
<bart416>
Modules can be PCBs
<bart416>
You nuts?
<bart416>
We're with 7 people
<bart416>
It'd take us months
<azonenberg_work>
Not really
<azonenberg_work>
Do the design on paper, maybe start with HDL and hand synthesize
<bart416>
Keep in mind we also have classes
<azonenberg_work>
then design a bunch of logic cells
<bart416>
I meant VLSI
<azonenberg_work>
cut and paste to form a reasonable (though perhaps not optimal) placement
<lekernel>
you'd need inane amounts of transistors
<azonenberg_work>
draw out routing
<lekernel>
4 bits could be feasible, but 16 ...
<azonenberg_work>
You dont draw each transsitor by hand
<bart416>
That'd take months in the bit of time we have though azonenberg
<bart416>
easily
<lekernel>
you'd need a cabinet
<bart416>
Yes, we will need a cabinet
<bart416>
that's the point
<azonenberg_work>
lol
<bart416>
We want to prove a professor wrong
<azonenberg_work>
Why not use 7400 chips
<bart416>
lol
<azonenberg_work>
... oh
<azonenberg_work>
lol
<azonenberg_work>
Thats a worthy excuse
<azonenberg_work>
i've done crazy things to prove faculty wrong
<bart416>
Cause with 7400 chips it's just stupid and anybody can do it
<bart416>
With 7400 series it takes almost no skill to make a small functional CPU
<azonenberg_work>
Like doing full functional programming (including passing a function as an argument to another function) in C
<azonenberg_work>
when he said it wasnt possible to do functional programming
<azonenberg_work>
Or writing an entire file system emulator (including the command line argument parsing) in x86 assembly
<azonenberg_work>
3000 lines in two weeks, including other homework
<azonenberg_work>
Or implementing an algorithm for solving the Towers of Hanoi puzzle (algorithm given to us) in x86 (which was the assignment)
<azonenberg_work>
But doing it in 19 instructions
<azonenberg_work>
when he said <20 was impossible
<bart416>
We had a fun one
<bart416>
Random dice throw generator
<bart416>
But only 2 d latch flip flops
<bart416>
Not as easy as it looks
<bart416>
(and it has to be able to hold a *random* value and be able to reset)
<bart416>
Using only digital logic
<bart416>
And you're not allowed to make new flip flops
<azonenberg_work>
Random number generator
<azonenberg_work>
Using two dff
<bart416>
The random generator is easy
<bart416>
Just use the system clock
<bart416>
that was available
<azonenberg_work>
Ok, if it has one
<azonenberg_work>
But two dff
<azonenberg_work>
for six values
<azonenberg_work>
you only have two bits?
<bart416>
It's possible weirdly enough
<azonenberg_work>
Oh, i believe you
<azonenberg_work>
i'm curious now
<azonenberg_work>
was it a dynamic state?
<bart416>
I never found it myself either
<azonenberg_work>
three bits, two in flipflops and one in motion?
<bart416>
I think he used the clock and somehow locked it as the final bit
<azonenberg_work>
like a circular shift register
<azonenberg_work>
crossed with a delay line
<azonenberg_work>
Just caught my pipelining bug
<azonenberg_work>
The latest one, at least
<azonenberg_work>
Subject: test program busy-waits on UART data ready, then reads byte, adds one, echoes out uart
<azonenberg_work>
repeats forever
<azonenberg_work>
Symptom: after processing 16 bytes (depth of the FIFO) it goes nuts and starts echoing the same value over and over
<azonenberg_work>
Eventually traced it to a bug where issuing a conditional the clock after a memory read would give an incorrect value if you used the result of the memory read
<berndj>
bart416, cutting mylar tape?
<bart416>
What about it berndj?
<berndj>
azonenberg_work, i've actually got a pipe dream of a fully trustable computer that's consist of *only* 74*00's
<mrdata>
lol
<berndj>
maybe not quite as trustable as relays as switching elements
<bart416>
Prepare for a very expensive project berndj :P
<mrdata>
"fully trustable"!
<berndj>
yes, a bit like "a little bit pregnant" :-/
<berndj>
bart416, i was referring to your no-software layout
<bart416>
How does that relate to mylar tape?
<azonenberg_work>
needs to get some kapton tape
<bart416>
We have enough breadboards at college to model an entire x86 cpu on them I think
<azonenberg_work>
bart416: lol
<azonenberg_work>
maybe an 8086
<azonenberg_work>
not an i7 :p
<berndj>
bart416, i thought that's how they did 4004-era chips
<bart416>
azonenberg, uhm the professor has a few cabinets in his office filled with boxes with nothing but breadboards...
<berndj>
and 8086 was about 35000 transistors IIRC, is that an "insane" number?
<azonenberg_work>
berndj: if you are going to do that
<bart416>
35000, meh
<azonenberg_work>
Design custom PCBs for each 7400 chip
<azonenberg_work>
Have a few dozen of each sent out
<azonenberg_work>
s/dozen/hundred
<azonenberg_work>
and load them up with SOT23 mosfets
<berndj>
azonenberg_work, yes, i was going to do it like that, have an "adder" board that gets reused a few times etc
<mrdata>
what would a MEMS pressure sensor look like?
<azonenberg_work>
s/7400/4000
<bart416>
I'd guess a sort of membrane ish structure
<berndj>
oh, but i'd make it a (super slow) bit slice processor, taking 16 cycles to do a 16-bit ALU op
<azonenberg_work>
mrdata: Thats like saying what would a car look like
<azonenberg_work>
It deends completely on the design
<azonenberg_work>
parallel membranes is one option
<bart416>
and using the capacity between the membranes as reference
<azonenberg_work>
Yeah
<azonenberg_work>
That would be my first thought
<bart416>
Looks the easiest way to go about it
<azonenberg_work>
i'd do it from two bonded wafers
<bart416>
But there might also be materials that change conductivity based on pressure I'd guess
<berndj>
if you used mosfets i guess you could have PCBs with nothing but transistors on them, right?
<berndj>
no resistors for bias etc
<azonenberg_work>
berndj: yes
<azonenberg_work>
Do CMOS
<azonenberg_work>
sot23 fets
<berndj>
how many SOT23 could you fit on a board?  on the order of 1000?
<azonenberg_work>
berndj: i was thinking making them 4000 series actually
<mrdata>
likes the parallel membranes; how hard would that be to make?
<azonenberg_work>
a wide (0.6 inch) dip14 etc
<azonenberg_work>
but if you want to do more complex modules thats fine
<azonenberg_work>
mrdata: Hmm
<azonenberg_work>
Let's see, we need a framework
<mrdata>
ok
<azonenberg_work>
two parallel membranes with an air gap between them
<mrdata>
sure
<azonenberg_work>
Both conductive, and insulated from their surroundings
<berndj>
azonenberg_work, ooh, you mean making little modules out of 7400-only, that emulate the other common logic functions?
<azonenberg_work>
And not touching
<azonenberg_work>
berndj: i was saying to make a DIP14 sized PCB with a few dozen sot23 (wide dip)
<berndj>
oh, lol
<azonenberg_work>
for a 4x 2NAND etc
<mrdata>
how small could it be made? what equipment would i want, to fab these?
<bart416>
mrdata, you could do this fairly large scale actually
<azonenberg_work>
mrdata: Well, let's see
<berndj>
hmm, to make a 7404 you'd need 12 transistors; can you fit them all?
<azonenberg_work>
Bonded wafers is something i havent looked into
<bart416>
azonenberg, I'd do this large scale
<bart416>
Take mylar
<bart416>
Space it slightly
<bart416>
so you have maybe a mm in between
<azonenberg_work>
bart416: i am thinking mems:p
<bart416>
yeah, but if you have to make it at home
<azonenberg_work>
Actually a pressure sensor would be a cool project once i do the comb drive
<mrdata>
yes
<azonenberg_work>
let me see, i read an interesting paper on making membranes by KOH etch of silicon
<azonenberg_work>
with heavy boron doping as an etch-stop layer
<azonenberg_work>
I have a slightly different idea
<azonenberg_work>
Bottom wafer is the carrier
<azonenberg_work>
the die has a ground terminal on it
<azonenberg_work>
and a big conductive disk
<mrdata>
is thinking about the size of an LED
<azonenberg_work>
mrdata: yeah, thats doable
<azonenberg_work>
So i was thinking of having a copper membrane
<azonenberg_work>
Deposited over silicon
<azonenberg_work>
then you etch the silicon out from under it
<azonenberg_work>
leaving it around the edges to support the membrane
<azonenberg_work>
you then place this framed membrane over another, stationary, conductor
<azonenberg_work>
apply pressure to the hole the membrane is in
<azonenberg_work>
and it will bow down
<azonenberg_work>
reducing plate separation
<mrdata>
yes
<mrdata>
and how would you etch the silicon?
<azonenberg_work>
KOH, thats easy
<azonenberg_work>
the harder part is masking it
<azonenberg_work>
Anyway so the thinking is
<azonenberg_work>
Bottom wafer, cover in copper
<azonenberg_work>
attach a ground terminal to the copper
<azonenberg_work>
s/wafer/die
<azonenberg_work>
Top die, cover top side in copper
<azonenberg_work>
flop over, put etch mask on bottom (material tbd)
<azonenberg_work>
put circular hole in the middle of this mask
<azonenberg_work>
oh, when you cover the top die in copper
<azonenberg_work>
do it over thermal oxide
<azonenberg_work>
So you have a circular hole in the mask
<azonenberg_work>
then you KOH through the top wafer from bottom up
<azonenberg_work>
This leaves us a big silicon die
<azonenberg_work>
with copper over the entire top surface
<azonenberg_work>
insulated from the silicon
<azonenberg_work>
by an oxide layer
<azonenberg_work>
the center of the die is just a copper film with nothing under it
<azonenberg_work>
thats our sensing element
<azonenberg_work>
Then we bond this to the original bottom die
<azonenberg_work>
hook a wire up to each copper laye
<azonenberg_work>
r
<azonenberg_work>
Bonding the dies together is a TBD problem
<azonenberg_work>
make sense?
<mrdata>
kind-of
<azonenberg_work>
the two unsolved problems in that process as far as i'm concerned are how to mask the KOH etch
<azonenberg_work>
and how to attach the wafers to each other
<azonenberg_work>
the second i havent looked at much
<azonenberg_work>
the first is something i am actively exploring
<mrdata>
i've etched aluminum with NaOH
<mrdata>
but havent etched any silicon
<azonenberg_work>
mrdata: NaOH or KOH is simple enough to use, they are very similiar
<azonenberg_work>
The hard part is masking them
<mrdata>
yes
<azonenberg_work>
As they eat photoresist (among other things)
<mrdata>
saponification, yeah
<azonenberg_work>
So you basically need a metal or oxide hardmask
<azonenberg_work>
and they eat SiO2 as well - around 40x slower than Si but its a nontrivial rate
<azonenberg_work>
normally they use silicon nitride but thats hard for an amateur to make
<mrdata>
do they eat vinyl?
<azonenberg_work>
mrdata: not sue
<azonenberg_work>
never seen characterizatinos of that reaction
<berndj>
do pretty much all SOT23's have the same pinout?
<mrdata>
wouldnt assume so
<berndj>
or rather, is it less of a mess than through-hole devices