<xiangfu>
not finish yet. so the git is may not sync with cvs.
<kristianpaul>
ah..
<xiangfu>
kristianpaul, I use git for weeks. modify. then copy to rtems.cvs and re-compile. :)
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<cladamw>
( rc3's yield ) still 79pcs, but just fixed another 3 sets except PHY id/midi/crc not tested. so yield will soon go over from 80 to maybe 82 sets.
<wpwrak>
kewl. we'll only have the ones with the botched FPGA left :) the ones that sometimes enter hectical reset oscillation
<cladamw>
yeah... still no further idea on reset oscillation likes 0x32. :)
<xiangfu>
cladamw, I still not fix the boot.bin buy. sorry.
<xiangfu>
cladamw, the PHY ID I needs ask Sebastien.
<cladamw>
xiangfu, no sorry. I was thought it's easy. :)
<xiangfu>
CRC is a strange error. I tried many method. it maybe ALIGN problem.
<xiangfu>
CRC BUG is like. all other test is working. only when press 'a -- tests_images' it will hang the system.
<cladamw>
xiangfu, for those packed rc3, i can just directly update it without crc testing. Since I can surely those m1 h/w worked pass already. For remaining new boards without f/w, i can temporarily skip phy id/midi/crc tests. No problems. :-)
<wpwrak>
cladamw: (0x32) i think it's simply a damaged fpga. maybe ESD, maybe excess heat.
<cladamw>
wpwrak, okay... the worse case that I remove fpga then remount it. not decided yet. :-)
<wpwrak>
cladamw: are you confident about reworking such a large BGA ? well, it's probably fun to try and see how far you can take things :)
<wolfspraul>
wpwrak: we should go watch some professional reworkers in factories, you would be *amazed*
<wolfspraul>
our hands are magic
<wpwrak>
wolfspraul: yeah,. i've seen some crazy rework when we did the hxd8 tear-down experiments
<cladamw>
bad now we( me and smt vendor)'ve not made specific stencil for our spartan-6 484 balls/apertures. This I'll do soon.
<wolfspraul>
just think what a pianist is able to do after 10+ years or more of training for hours each day
<wpwrak>
wolfspraul: it was fun. i just had to point at a chip, and two minutes later it was gone, and the board still worked (and, of course, still faithfully showed the bug)
<cladamw>
to make a "small" square stencil with 484 apertures.
<wolfspraul>
actually I think precision reworking is valuable not just as a way to bring a product back to working or even sellable state, but also to aid in tracking down yield problems
<wolfspraul>
so any manufacturer is well advised to not let that capability sink too low, otherwise they will have yield problems sooner or later
<wolfspraul>
just my thinking
<wpwrak>
hmm, maybe. it has great value for R&D, of course. so at least from that angle, i'd agree that this is a skill worth nurturing.
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<cladamw>
wpwrak, ( rc3, 0x32 ) forgot to tell you. I found that actually BTN2 level is 2V which is not correct so that causing reset oscillation( tp36/tp37 to randomly pulse).
<lekernel_>
BTN2? the button?
<cladamw>
wpwrak, now the BTN2 level (i.e. is the middle btn's ctrl signal) works well though. :-) This result is done after I "heavily heat fpga BTN2 area by blow air @ 325 ℃" and blow air in four edges of fpga too. I was so much "stupid" & "brave" without thinking too much. Just took risk. :-)
<cladamw>
lekernel_, yes. the BTN2 is the signal to activate bootup procedure. :-)
<cladamw>
This result makes me strongly doubted and thought that it's a mix composed by flux and cleaning liquid stocked under BTN2 ball area during several times rework nearby 'reset circuit' to cause it.
<cladamw>
just guessed in this way. I'll let it run overnight and keep an eye on that level again. :-)
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<xiangfu>
the boot.bin problem is the crc32 fault. :(
<GitHub82>
[autotest-m1] sbourdeauducq pushed 1 new commit to master: http://git.io/q6IF8A
<GitHub82>
[autotest-m1/master] Fix new compiler warnings - Sebastien Bourdeauducq
* xiangfu
have the same patch not push.
<GitHub139>
[autotest-m1] sbourdeauducq pushed 1 new commit to master: http://git.io/2tmE_Q
<GitHub139>
[autotest-m1/master] MIDI: support new uart core, correctly this time - Sebastien Bourdeauducq
<GitHub69>
[autotest-m1] xiangfu pushed 1 new commit to master: http://git.io/PIBQuw
<GitHub69>
[autotest-m1/master] some variable names cleanup - Xiangfu Liu
<GitHub68>
[autotest-m1] xiangfu force-pushed master from fb05b90 to 50d40bb: http://git.io/FNP5fw
<GitHub68>
[autotest-m1/master] some variable names cleanup - Xiangfu Liu
<xiangfu>
sorry. should be const. not static.
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<whitequark>
will a synthesizer eliminate common subexpressions or I should do that myself by defining explicit wirs ?
<whitequark>
*wires
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<kristianpaul>
whitequark: yes
<wpwrak>
kristianpaul: "tea or coffee ?" "yes" :)
<lars_>
wpwrak: "teoffe"
<kristianpaul>
wpwrak: aromatica ;-)
<kristianpaul>
Fines herbes tea english name is i think
<kristianpaul>
lol
<kristianpaul>
you always making laught of me :)
<kristianpaul>
whitequark: yes you should define constraints i meant
<whitequark>
kristianpaul: ah. thanks.
<whitequark>
then a lot of my code is horribly ineffecient :/
* whitequark
goes to rewire the whole pipeline 4th time this day
<kristianpaul>
it depends what you want to do anyway?
<kristianpaul>
if still the cpu think i think icarus and some prints will be more that enought perhaps? or the a test bench with gtkwave to confirm results?
<whitequark>
kristianpaul: I'm not sure if the subexpression elimination will be visible as waveforms
<whitequark>
it's more of FPGA space (and speed) concern
<whitequark>
well, RTL looks horrible, so I guess I'm doing that wrong
<lars_>
rtl looks always horrible ;)
<whitequark>
lars_: in the more clean parts of my design, rtl is exactly like it was wired by a person
<lars_>
and what are you doing in the not so clean parts?