<azonenberg>
"These pages assume a good understanding of Xilinx's Virtex FPGA architecture and of the Haskell lazy functional programming language. The number of people that know about both can easily fit inside a medium sized elevator"
<azonenberg>
Looks interesting but i question whether it's too complex to be of any use lol
<barbu-uucp>
you find it complex?
<azonenberg>
I understand what they're doing
<barbu-uucp>
it's not any worse than your pipelined adder :)
<azonenberg>
i just think that often you dont care about placement
<azonenberg>
But OTOH, mixing that with verilog or vhdl
<azonenberg>
for the most speed critical parts of the circuit
<azonenberg>
Might well be worth doing
<barbu-uucp>
what could be cool would be a high-level placer
<barbu-uucp>
something that operates on top of lava and automatically generates the lava-level placement constraints
<azonenberg>
HmmI definitely want to play with it, thats for sure
<azonenberg>
Is there a back end for spartan chips?
<barbu-uucp>
though lava itself already has a good deal of functions that generate placements
<barbu-uucp>
so it's not _that_ bad :)
<barbu-uucp>
no, I don't think so. you'd have to write it :)
<barbu-uucp>
some things have changed, e.g. the carry chains are more complex now
<azonenberg>
yeah
<barbu-uucp>
and 6-LUT architectures can build efficient ternary adders with one chain
<barbu-uucp>
so the adder tree example needs some revamping
<azonenberg>
Well, i am definitely going to fool around with it though
<azonenberg>
As well as manually doing low level (LUT and CLB based) FPGA dev at some point
<azonenberg>
I intend to learn the architecture inside out
<barbu-uucp>
azonenberg: you can also try to combine Lava with a DIY router (not too hard to do using the XDL descriptions) and the Recobus bitstream generator
<barbu-uucp>
lava to bitstream in 100ms, without any xilinx tool :)
<azonenberg>
lol
<azonenberg>
I do want a free toolhain
<azonenberg>
And one optimized for extreme performance wouldn't hurt
<azonenberg>
Something to look into when i have free time, perhaps
<azonenberg>
But I have a doctoral thesis in *computer science* to finish first
<azonenberg>
Maybe then i can think about doing one in EE :p
<barbu-uucp>
I wonder how hard it would be to run Haskell on the LM32
<barbu-uucp>
cpython is messy, lots of dynamic code loading
<barbu-uucp>
ruby is super easy
<azonenberg>
No idea, i havent used lm32
<azonenberg>
I'm actually writing my own softcore optimized for my specific workloads
<azonenberg>
2-way superscalar barrel processor
<azonenberg>
16 threads, it issues two instructions from each one in a round-robin fashion
<azonenberg>
then goes back and issues two from the first thread again etc
<azonenberg>
that allows a 16-stage pipeline with no stalls
<barbu-uucp>
well, the problem is actually not LM32 itself, it's more about the operating systems
<azonenberg>
in reality some of the FPU is 32 stages so i need to have one delay slot in which you can't use the output of the fdiv/fsqrt or it'll stall
<barbu-uucp>
python happily calls dl*() all over the place, that neither RTEMS or Linux implements properly
<azonenberg>
lol
<azonenberg>
I havent even started to think about the OS i'd run on this guy
<azonenberg>
But it'd have to be hardware multithreading aware
<azonenberg>
My roommate says that lava looks like the C of HDLs
<azonenberg>
as in, getting close to the architecture for maximum performance
<azonenberg>
while still maintaining some level of abstraction for ease of development
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