<adamgreig>
rtt min/avg/max/mdev = 0.053/0.057/0.105/0.008 ms, ipg/ewma 1.452/0.056 ms
<adamgreig>
57µs rtt though
<tnt>
:)
<adamgreig>
not bad for a 100Mbps link
<Bob_Dole>
remember when hardware accelerated IP-stacks with proprietary firmware were being sold to consumers because pentium 4's could get bogged down on handling gigabit ethernet?
<adamgreig>
and now 500 lines of python and a £4 fpga eats it up ;)
<Bob_Dole>
not sure if they handled udp or just tcp
<adamgreig>
i suspect those implemented a lot more of tcp/ip than my thing does though
<adamgreig>
this is definitely not fully compliant ;)
<Bob_Dole>
thinking about it, I wonder if the folks still nursing along their amigas and putting them on the net would appreciate hardware accelerated tcp/ip stacks...
<Bob_Dole>
the C64 folks like the ESP mcu ones at least.
<gruetzkopf>
we amiga people jumped to "plain ip over printer port" for the cheapo solution
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<pie__>
extra credit for if youre just printing IP packets
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<jn__>
pie__: then you have a IPoAC gateway
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<azonenberg>
Bob_Dole: i'm doing hardware accelerated TCP for 1/10GbE
<azonenberg>
But it's not because the CPU is too slow, it's because it's on an FPGA board that *has* no cpu :p
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<cr1901_modern>
IME tcp/ip stacks aren't the thing that need hardware accelerating (I can live with a 10Mbps link); it's the crypto that needs accelerating and Idk a good solution for SSL other than "use a Pi/some other SBC several times more powerful than the vintage machine to do it for you"
<cr1901_modern>
And that's no fun
<azonenberg>
cr1901_modern: most stm32s have hardware AES
<cr1901_modern>
Slowest machine I've heard of doing SSL under it's own power is a 25MHz 68030
<azonenberg>
curve25519 isnt too cpu hungry and you only need to do it when you open the link
<cr1901_modern>
azonenberg: Well certainly I'm not against like an ISA card crypto accelerator :).
<cr1901_modern>
I just don't want to cheat w/ a Pi/SBC
<azonenberg>
lol
<cr1901_modern>
Assign two Port I/O locations, feed it your input on one port, read the status on the same port, and read out the result on the second port a few hundred to few thousand clk cycles later
<adamgreig>
woo, all my packet loss was due to poorly thought out cdc
<adamgreig>
rtt min/avg/max/mdev = 0.041/0.054/0.247/0.009 ms, ipg/ewma 0.063/0.057 ms
<adamgreig>
who would have thought "DummyAsyncFIFO" might not be legit
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<mkdir>
does block ram just act like cache
<mkdir>
or rather, how does cache differ from main memory
<pie__>
...distributed memory sounds more appropriate, depending on what youre doing? (i'unno)
<adamgreig>
are you asking in general or for fpgas or what?
<adamgreig>
on a typical desktop computer, main memory is separate on the motherboard, made from DRAM, so is slower but cheaper and smaller for the same capacity compared to SRAM which you typically use for cache
<adamgreig>
but there's probably several layers of SRAM cache, getting slower and bigger the closer to the dram it gets
<adamgreig>
on an fpga.. it's all whatever you want it for
<adamgreig>
cache is just one thing you might use memory for
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<mkdir>
thanks for your response, well i'm just curious how fetching items from block ram is different than fetching items from main memory
<mkdir>
is it similar to fetching items from cache i.e very fast
<tpw_rules>
depends on the memory
<mkdir>
fetching / reading data
<tpw_rules>
block ram is just ram on the fpga
<adamgreig>
typically accessing block ram is fast, it's usually just you put an address on the address pins and 0-2 clock cycles later you get data on the data pins
<tpw_rules>
but there's nothing stopping you from wiring up an equally capable chip to the fpga
<adamgreig>
compared to external DDR DRAM where you have to do a whole bus transaction to request data, it's usually going to be quicker
<mkdir>
i see
<mkdir>
i guess the reason i'm asking from a cpu perspective (i.e main memory and cache structure) is because im trying to learn fpgas
<adamgreig>
the distinctions are between sram and dram (sram is faster but lower capacity), and onboard the fpga or not (onboard is easy but you often don't have much of it)
<mkdir>
currently do firmware only :9
<tpw_rules>
block ram is whatever you want it to be. in most of my designs, it's all the ram the design uses, since it's enough
<Bob_Dole>
dram is "slow", and SRAM is expensive to get even a few MB of truly fast SRAM.
<tpw_rules>
but i only do lame small designs
<adamgreig>
but the fpga is sort of made of sram too
<mkdir>
can block ram be configured as sram or dram
<mkdir>
os it only one type?
<adamgreig>
no, sram or dram is defined by the hardware silicon
<tpw_rules>
but you do get all kinds of config operations
<adamgreig>
they're physically different ways to store data
<tpw_rules>
how wide, how deep, how much latency, how many ports
<Bob_Dole>
sram is 6 transistors, dram is 1-3 transistors and a capacitor
<mkdir>
i see
<mkdir>
thanks guys, i have to read more now before i ask more questions
<Bob_Dole>
the dram cells need to be a lot more complicated because of the need to keep the capacitors refreshing their charge, and being able to handle the reads and replenishing the cap after, and then all the extra stuff and features added since. an SRAM will just maintain itself as long as it has power and is always ready to be read or written.
<Bob_Dole>
s/dram cells/dram memories/\
<tpw_rules>
i would be surprised of m/any fpgas had block dram
<Bob_Dole>
edram is a thing so it'd be possible
<adamgreig>
you can get fpga+hbm in one package
<adamgreig>
but it's not what you'd call 'block ram' really :P
<Bob_Dole>
but adds fabrication cost, think it requires some slightly different production processes than is suited for large logic chips? I think the xbox 360 used a few hundred MB of it.
<Bob_Dole>
I mean the edram, not hbm obviously
<Bob_Dole>
(not that HBM is anything beginning to resemble cheap.)
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<daveshah>
There are a few FPGAs with a bog standard DRAM (SDRAM, DDR2 or PSRAM) in the package
<daveshah>
Gowin and Anlogic have them iirc
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<Thorn>
why is there never on-chip dram though? does it require completely different process than logic or something?
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<sorear>
Thorn: yes. DRAMs need a bunch of extra steps to create large capacitors