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<whitequark> ZipCPU: HA
<whitequark> I found an *excellent* bug with formal verification just now.
<whitequark> incredibly tricky, and only active in one obscure corner case.
<zkms> whitequark: what was the bug?
<whitequark> zkms: replacing the last pushed entry in a non-power-of-2 depth FIFO in the case where producer pointer just wrapped out would overwrite the wrong entry
<whitequark> it's great because both NPoT depth FIFOs and especially replace are very rarely used features
<pie___> whitequark, feel the powaaa
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<pie___> im waiting for the day wq writes a theorem prover
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<whitequark> no thats companion_cube's domain
<whitequark> i cant even prove jack shit
<azonenberg> whitequark: what would you use a NPOT fifo for?
<azonenberg> i cant remember ever using one
<azonenberg> largely because both asic and fpga sram tends to be PoT depth
<azonenberg> so rounding up to the next PoT is free
<pie___> smoke PoT every day?
<whitequark> azonenberg: you can make a FIFO out of 3 BRAMs
<whitequark> if you configure them for different aspect ratio
<egg|egg> companion_cube?
<whitequark> that would be NPoT
<whitequark> I am not sure if Yosys can infer that but it is a valid and desirable use case
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<the_new_lfsr> hello world xD I am trying to know more about FPGA and computing hardware, any suggestions about forums, fpgas to buy all will welcome!
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<daveshah> the_new_lfsr: welcome! anything in particular you are interested in? if totally new to FPGAs I'd recommend an iCE40 board because they have a stable open source toolchain and plenty of tutorials
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<etrig> what's the roadmap for supporting anlogic parts in nextpnr? great to see mmicko's work!
<the_new_lfsr> daveshah (i don't know how to cite people hahaha) I have done a research involving fpgas where I built some hardware neural networks and also learned about stochastic computing, and VHDL as the HDL. The problem is that that particular FPGA and its toolchain was completely obsolete... (I was debuging things with signalTap)
<daveshah> The convention on IRC is usually username and a colon
<daveshah> Sounds like cool projects
<daveshah> Unfortunately the current state of open source tools means VHDL support is very limited
<the_new_lfsr> Now I would like to keep learning about hardware development using all the free software I can for being able to introduce myself to professional hardware development while I do a non-related thesis on quantum dots
<daveshah> Almost everything at the moment is Verilog with a small but increasing subset of SystemVerilog support
<the_new_lfsr> daveshah: thankyou haha
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<the_new_lfsr> my biggest disadvantage is that I'm not a computer engineer, I'm physicist
<the_new_lfsr> so, I have a ton to learn :)
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<daveshah> Sounds like you have some background in HDL though, which is great
<the_new_lfsr> I heard that Systemverilog is almost as verilog, but more flexible. I have no problem in learning verilog, at least I do understand concurrency an digital circuits
<the_new_lfsr> thanxs
<daveshah> Yes, that's the important thing, particularly for people coming from a sequential software background
<the_new_lfsr> so, any forums, webpages, rss feeds, I would be very gratefull
<kc8apf> the_new_lfsr: experimental or theoretical?
<daveshah> The TinyFPGA and its forum and community is quite good https://tinyfpga.com
<the_new_lfsr> yeah, I used only fortran during my degree... When I learnt python I went crazy wuth all that "new" stuff I was suddenly able to do
<the_new_lfsr> kc8apf: what do you mean?
<daveshah> There's also the mystorm forum and boards https://forum.mystorm.uk
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<the_new_lfsr> thanks!
<kc8apf> the_new_lfsr: what kind of physicist?
<the_new_lfsr> ahh ok
<the_new_lfsr> I am a theoretical physicst, though there is usually a misunderstandin about what they are. In my case, I do research about quantum dots. I simulate them to predict the electronic mobility and light absorbance to see if they would fit as solar cells
<kc8apf> I've had the privilege of working with quite a few physicists turned software/hardware engineers
<the_new_lfsr> yeah, I am seeing lots of coleagues going to work with computers, maybe not as engineers but with big data, artificial intelligence and so
<kc8apf> very cool
<kc8apf> physics seems to develop a problem-solving skillset that translates very well to tricky computing problems
<the_new_lfsr> I allways liked digital circuits and electronics in general, and I now see myself working at something related
<the_new_lfsr> yes, I heard that. I hope will work well in hardware too
<kc8apf> specifically, physicists seem to understand how to develop controlled experiments to figure out what contributes to a surprising result in a complex system
<the_new_lfsr> though computer engineers have an incredible workflow
<the_new_lfsr> I am still a toddler in github, and it would be amazing that my research team would understand it. We would be so much more efficient!
<kc8apf> :) very true
<kc8apf> most engineers would be more efficient if they used git/ci/cd workflows
<the_new_lfsr> ci cd dosen't ring me a bell hahah
<the_new_lfsr> what do you do for a living?
<kc8apf> continuous integration and continuous delivery
<the_new_lfsr> ahh I think I catch the idea
<kc8apf> software engineer currently working on enterprise security software
<gruetzkopf> yeah, we "computer" people are privileged that building the tools to better our workflow fits our scope of activities
<kc8apf> gruetzkopf: I'm continually suprised that VCs and tech leaders don't understand that
<the_new_lfsr> gruetzkopf: totally
<kc8apf> the_new_lfsr: though I've had a varied career through software/hardware
<the_new_lfsr> I heard that security is the big thing for searching for a job right now
<kc8apf> yes. not sure it's my scene though
<the_new_lfsr> kc8apf: I have a question for you then. I observed that when connected here, it displayed my public IP. Isn't that a dangerous thing?
<the_new_lfsr> [not sure it's my scene though] what does interest you most?
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<gruetzkopf> i somehow fell into doing test and measurement stuff for safety applications..
<kc8apf> you share your public IP with every site you connect to. Why would it be any more dangerous here?
<the_new_lfsr> because it is visible to everybody connected. I don't know much of this, but, if I connect to, say, twitter, other users don't have access to that information. Do they??
<the_new_lfsr> By the way, I have good vibes about this community, I was just asking
<kc8apf> I enjoy building tools and infrastructure. Especially things that dramatically improve developer experience and/or move an industry in a new direction.
<kc8apf> I'm hoping to find a way back into having a job working on open-source FPGA/ASIC tools
<the_new_lfsr> yeah, that would be super cool as a job
<kc8apf> public IPs are a bit like vehicle number plates. Generally, knowing it doesn't provide much information.
<the_new_lfsr> thanks for the info people, see you around!
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<tnt> It's nowhere as complete and pro looking as Boneless arch manual but hopefully it's clear enough to get an idea of where I'm going :p https://gist.github.com/smunaut/dac7a096add6bcdb5b70f0e205e4d16d
<whitequark> SPRAM-only?
<tnt> well, one SPRAM for program and one EBR for data.
<whitequark> oh i see, that's a rather different design
<tnt> yeah, very different design than boneless :) (if it hadn't been, I wouldn't have bothered)
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<tnt> wth ... I instanciate a SB_DFFESR and yosys goes and alters it ....
<whitequark> yes
<whitequark> why is that a problem?
<whitequark> it's just like opt_lut changing your SB_LUT4 instantiations
<tnt> Because it changes the control set (CE / R) and means they don't fit in the same LC anymore.
<tnt> and since I'm hand placing stuff ... that fails.
<whitequark> (* keep *) iirc
<daveshah> I don't know if that stops Yosys from changing things
<daveshah> It's more to stop it removing them altogether
<daveshah> I'm not sure why a DFFESR would be modified, do you have non zero init values going on?
<whitequark> actually, now that i look closer
<tnt> dont_touch="true"
<whitequark> which pass is doing that?
<whitequark> I can't find it
<daveshah> I still can't think why that pass would touch an instantiated DFFESR
<whitequark> because it runs late in synthesis
<tnt> daveshah: mmm, it might have been a dffe actually.
<daveshah> Must have been
<whitequark> oh, ESR
<daveshah> That pass won't touch FFs that already have S/R
<tnt> yeah, it's a dffe that got changed to dffesr
<tnt> my bad, sorry for the confusion, I got it the other way around.
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