Vincenttl has quit [Quit: Connection closed for inactivity]
azonenberg_work has quit [Ping timeout: 245 seconds]
azonenberg_work has joined ##openfpga
azonenberg_work has quit [Ping timeout: 258 seconds]
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
ZipCPU has quit [Ping timeout: 258 seconds]
ZipCPU has joined ##openfpga
genii has joined ##openfpga
unixb0y has quit [Ping timeout: 250 seconds]
unixb0y has joined ##openfpga
dj_pi has joined ##openfpga
genii has quit [Remote host closed the connection]
azonenberg_work has joined ##openfpga
pie_ has quit [Quit: Leaving]
dj_pi has quit [Ping timeout: 245 seconds]
plantdemon is now known as catplant
Bob_Dole has quit [Quit: Leaving]
Bob_Dole has joined ##openfpga
rohitksingh_work has joined ##openfpga
Flea86 has quit [Quit: Goodbye and thanks for all the dirty sand ;-)]
Bike has quit [Quit: Lost terminal]
_whitelogger has joined ##openfpga
Flea86 has joined ##openfpga
ayjay_t has quit [Read error: Connection reset by peer]
ayjay_t has joined ##openfpga
rohitksingh_work has quit [Ping timeout: 258 seconds]
ayjay_t has quit [Read error: Connection reset by peer]
ayjay_t has joined ##openfpga
futarisIRCcloud has joined ##openfpga
rohitksingh_work has joined ##openfpga
rohitksingh has joined ##openfpga
rohitksingh has quit [Ping timeout: 245 seconds]
rohitksingh has joined ##openfpga
gruetzkopf has joined ##openfpga
<RaYmAn>
daveshah: Is there any sane way to use libtrellis apis to modify a config word in a bitstream? I'm trying deserialize, modify, serialize step, but it's not quite obvious to me how to actually modify it properly
<RaYmAn>
hm, okay, so that' similar to what I'm doing. I guess I'm on the right path then :) (although, using the C++ api directly)
gruetzkopf is now known as gruetze
gruetze is now known as gruetzkopf
emka has quit [Quit: Connection closed for inactivity]
tmeissner has joined ##openfpga
sxpert has joined ##openfpga
nats` has joined ##openfpga
<sxpert>
nats`: yo
<nats`>
plop
<sxpert>
so, I was saying...
<sxpert>
a bunch of bmd devices use series 6
<nats`>
sure
<nats`>
but IIRC they switched all recent cheap one on artix 7
<sxpert>
I dunno what the teranex mini series use (yet), didn't get to purchase one yet
<nats`>
afaik BMD are not schematic open source
<nats`>
or are they ?
<RaYmAn>
daveshah: awesome, thanks! works :D wrt. the database format, what is the difference between ".config name value\nFXXBY FX2BZ...\n" and ".config name value\nFXXBY\nFX2Z\n..." - ecpunpack seems to interpret the two totally different
<sxpert>
nats`: nope
<sxpert>
nats`: not that can't be RE'd though
<nats`>
to b honnest I'm alway mixed on that topic
<nats`>
what is the effort to RE the board and to make a new one
<nats`>
I myself made on HDMI2 boardout of an artix 7
<sxpert>
true
<nats`>
and I'm not sure the effort to RE BMD is really interesting
<sxpert>
I see
<nats`>
if a lot of people are waiting for that maybe it worth the effort to make a PCI-E opensource board
<nats`>
you avoid a lot of license trouble and you could do it with more recent fpga when they will be supported on opensource toolchain
<nats`>
my 2 cents obviously but backed by some experience now
<sxpert>
ok
<sxpert>
makes sense
<sxpert>
much more work than blankslate
<nats`>
I started something really close for SDI 3 years ago but it was in cadence, seeing how kicad works now it could be done in kicad
<nats`>
in fact the main load is not in doing a board
<nats`>
it's really in the FPGA toolchain part
<nats`>
so if you take critical path you're farther away from serie 6 compatibility than serie 7
<nats`>
+ reverse of existing board
<sxpert>
I see
<sxpert>
and 7 is cheaper you say ?
<nats`>
it's alittle more complicated but from what I saw for same performance yes
<sxpert>
ok
<sxpert>
it's always more complicated ;)
<nats`>
basically you can have artix 7 with 6Gbps GTP starting at 30 or 40$ depends how you buy it
<daveshah>
RaYmAn: each line of a `.config` is one bit of the value
<nats`>
I'm talking about artix7 15T which is in fact a 50T
<daveshah>
so two bits on the same line means that logical bit maps to two physical bits
<nats`>
and with that you can really make a lot more than spartan 6 at same price
<sxpert>
I see
<RaYmAn>
daveshah: aha, so my meta fuzzer is broken then, thanks
<sxpert>
nats`: now I need to learn verilog I guess
<nats`>
verilog/vhdl/other pick your choice
<nats`>
are you a soft dev ?
<sxpert>
yeah
<sxpert>
mostly
<sxpert>
I tend to do hardware stuff that eventually blows up
<nats`>
hehe
<nats`>
anyway pick the one you prefere the things is to think differently in fact
<sxpert>
okk
<nats`>
if you understand well how to work with parallel sync/async etc.... it'll be a matter of days to read/write an other language
Vincenttl has joined ##openfpga
rohitksingh has quit [Ping timeout: 272 seconds]
<Flea86>
"<nats`> I'm talking about artix7 15T which is in fact a 50T" Though with defects, right? or not..
<gruetzkopf>
the smallest ECP5 with transceiver is <15$
<gruetzkopf>
in 1-count
<Flea86>
yeah
<Flea86>
gruetzkopf: Though the 5Gbit serdes ECP5 variant is closer to $18...
<gruetzkopf>
i need to build a test board
<gruetzkopf>
and check how well they bin them
<Flea86>
gruetzkopf: I've previously attempted to characterize my scope's capabilities, using a few engineering samples of the LFE5UM5G.. :)
<gruetzkopf>
ah :D
<gruetzkopf>
my approach to serdes protocols is a bit more "ah well, will work"
<Flea86>
Turns out Tek did not give me any free lunch above 1GHz.. Oh well.
<gruetzkopf>
don't have anything that can measure above 300MHz
<Flea86>
This scope has saved my arse in other ways tho
<Flea86>
gruetzkopf: I probably could've settled for 300MHz scope.
<Flea86>
if I could find one at a reasonable price here in .au
<Flea86>
This was two years ago now
Flea86 has quit [Quit: Goodbye and thanks for all the dirty sand ;-)]
<gruetzkopf>
.au is mode: hard in "used electronics"
rohitksingh_work has quit [Read error: Connection reset by peer]
<nats`>
ahh flea left
<nats`>
for the record no defect in the die because the placement and routing in the 15 are totally free in all the die only the volume of used logic will block the software
<nats`>
so they are perfectly working dies
<sxpert>
ah, so same die, and vivato limits how much you can configure of it ?
<sxpert>
obviously an opensource programming system would not care about those fake limits ;)
<nats`>
yep
<nats`>
dies or dice ?
<nats`>
I never know
<tmeissner>
dice I think ;)
<nats`>
thx, those words are really weird for a non native english speaker
<sxpert>
suppose there's a large price difference between the 2
<sxpert>
nats`: dies
Miyu has joined ##openfpga
<gruetzkopf>
dies, because we're not talking about gambling
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
<nats`>
felix_, will take a look later:)
<sxpert>
so, opensource 6G SDI In and Out ip blocks
<felix_>
someone else was making a pcie sdi card, not sure if that will end up being open source or if it's public info who worked on that
<felix_>
yeah, i'm still working on getting photonSDI ready, but didn't have as much time to work on that as i'd liked
<sxpert>
ah well
<sxpert>
doing things right takes time
<felix_>
doesn't move very fast, but it still moves ;)
<felix_>
yep
<sxpert>
looking for something like a to 8 input video mixer thing with multiview, 2 aux, and a stream to network output ;)
<felix_>
on the board: i still have maybe 15 todos for the next revision, but they are all in my personal todo list and not on github
<felix_>
oh, nice
<sxpert>
well I'm looking for that
<felix_>
synchronizing everything might be quite a pain though. would have been so much easier if sdi was packet based
<sxpert>
felix_: nah, you just need a common frame sync system not a big issue
<felix_>
yeah, if everything is synchronous to one studio clock, things get easier
<sxpert>
you need 1 frame of sync
<sxpert>
maybe 2
<felix_>
haven't done the bringup of the Si5342 yet, but that chip seemed to be exactly the one i needed
<sxpert>
dunno what that'd be used for in this contect
<sxpert>
context
<felix_>
the thing i'm not 100% sure about is if the gtp quad pll will lose lock when tracking the recovered clock. i've seen this configuration (no seperate crystal oscillator for the rx part) in an existing design, so with the pll bandwidth being low enough, it\ll probably work
<felix_>
clock generation and synchronizing on a reference signal
<felix_>
either sdi input or legacy empty video signal
<sxpert>
ah, erh, not sure you'd need that
<sxpert>
sdi is frame synched
<sxpert>
there's a certain "start of frame" bit combination
<felix_>
it's not packet based, so you have to synchronize clocks to be standard compliant
<felix_>
it'll likely work if you make the blanking one work longer or shorter though
<felix_>
oh and if you're looking into sdi, i;d strongly recommend looking at the itu recommendation. so much better than the smpte stuff...
<sxpert>
you have 2 modes possible
<sxpert>
either synched to a house clock, or everything is free running
<sxpert>
self-syncing
<felix_>
when having multiple sources with free running local oscillator that just output signals, you'll get timing drift between them though
tmeissner has quit [Quit: Leaving]
<felix_>
so after some time you'll either have to duplicate or drop a frame if you want to mix the two video signals together
<sxpert>
each device will sink it's clock to whatever signal comes in, unless there's multiple inputs in which case you generate your own clock
<sxpert>
when you have multiple input, you need a frame synchronizer on each of those inputs (that is a buffering system so that you can sync all those streams to a common clock
<sxpert>
which, at worst case, adds 1 frame delay
<felix_>
yep
<sxpert>
not a biggie
<felix_>
but if the frame rate slightly differs, you'll eventually have to drop or duplicate frames
<sxpert>
which won't show from the frame sync perspective
<sxpert>
things may become somewhat hairy if you try to handle sound delay at the same time
<sxpert>
you may have to drop a sample here and there
rohitksingh has quit [Ping timeout: 245 seconds]
<felix_>
yeah, audio is much more critical. if the clocks aren't phase-locked, you probably need to resample
<felix_>
dropping audio samples is much worse than proper resampling
<sxpert>
so the better solution is to have a house clock
<gruetzkopf>
^
<felix_>
yep
<jn__>
clock domain: house
<gruetzkopf>
i'm currently looking at SD-SDI
<felix_>
or just use avb that uses ptp for that. well, only problem is that avb seems to be not very alive :/
* felix_
intentionally doesn't support sd-sdi in photonsdi ;P
<sxpert>
gruetzkopf: sd-sdi is gone please stop
<gruetzkopf>
hello. i am gruetzkopf, i play with obscure 90s gear
<sxpert>
ahahaha
<gruetzkopf>
in this case: silicon graphics onyx2 with "DIVO" SD-SDI cards
<gruetzkopf>
(which support dual-link sd-sdi :P)
<felix_>
.oO(sd-sdi to railway adapter over mulitple multiplexed isdn lines?) *scnr*
<gruetzkopf>
SDI over SDH is commonly done
<felix_>
heh
<sxpert>
I've seen SDI over PDH ;)
Maya-sama has joined ##openfpga
<gruetzkopf>
netinsight makes gear for SDI-over-sdh iirc
<felix_>
the moment when you try to make a bad joke, but someone already implemented that /o\
<gruetzkopf>
also tunnels DVB-ASI, Ethernet and ISDN E1
Miyu has quit [Ping timeout: 244 seconds]
<sxpert>
ahmagad !
Miyu has joined ##openfpga
<sxpert>
then there's bbc's compressed SDI over IP
Maya-sama has quit [Ping timeout: 250 seconds]
ayjay_t has quit [Read error: Connection reset by peer]
ayjay_t has joined ##openfpga
pie_ has quit [Ping timeout: 260 seconds]
rofl__ has quit [Remote host closed the connection]
jcarpenter2 has joined ##openfpga
ayjay_t has quit [Read error: Connection reset by peer]
ayjay_t has joined ##openfpga
<gruetzkopf>
the minibnc-hd connector is cute though
m4ssi has quit [Remote host closed the connection]
rohitksingh has joined ##openfpga
rohitksingh has quit [Ping timeout: 244 seconds]
X-Scale has quit [Ping timeout: 245 seconds]
X-Scale` has joined ##openfpga
pie_ has joined ##openfpga
pie_ has quit [Remote host closed the connection]
pie_ has joined ##openfpga
pie_ has quit [Ping timeout: 240 seconds]
powerbit has joined ##openfpga
Bike has joined ##openfpga
Bike has quit [Client Quit]
Bike has joined ##openfpga
inoor has joined ##openfpga
GenTooMan has joined ##openfpga
Flea86 has joined ##openfpga
<nats`>
Flea86, related to earlier discussion
<nats`>
dies are not damaged
<nats`>
50t and 15/35T are valid working dies
<nats`>
you can check that because you can route/place everywhere with no limit but only the volume of logic/bram is limited by the software
<Flea86>
nats`: Ah, so crippled on purpose, like rigol ^^
<nats`>
yep
<Flea86>
To think I my Ohm board almost had an Artix on it :)