00:48 <pointfree> cr1901_modern: I'm not really saying one is more useful than the other. A FPGA or CPLD will have more regular structure and a more general design making it more beautiful, I suppose. That's all.

01:54 <pointfree> cool. So the CY8CKIT-059 does have a hard *USB* (uart). No UDB space will need to be wasted for just a uart connection. This only means I will need to write a USB driver.

02:44 <cyrozap> pointfree: The PSoC 5LP has a USB peripheral and two SCBs (which can both be used as UARTs), so if you use the SCB, you won't need to write any USB code.

03:02 <pointfree> cyrozap: That's great news. Are the SCBs documented anywhere? The Registers TRM returns zero hits for the keyword SCB or "Serial Control Block"

03:02 <pointfree> Looks like there are some docs for PSoC 4 SCB's.

03:03 <cyrozap> Oh, oops, I guess I was thinking of the PSoC 4...

03:04 <cyrozap> For some reason I thought there were hard macros for serial stuff in the PSoC 5LP, too

03:07 <cyrozap> Looks like there's one hard I2C peripheral, so while that's not exactly what you're looking for, you can use it to get data out of the chip

03:57 <pointfree> cyrozap: Yeah, what I ultimately want is something asynchronous like a uart.

03:57 <pointfree> I suppose it's also time to start looking into the PHUB.

03:58 <pointfree> Now that I can run code from the arm and all.

23:52 <cyrozap> Hey, azonenberg, I have a somewhat random question for you: to what extent can an FPGA build process be parallelized? i.e., can it only be done on a per-build basis (multiple builds running simultaneously in separate processes) or can the synth/techmapping/PAR steps have some parts run in parallel?