<azonenberg>
So I think i know what has to be done to continue work on the DAC implementation
<azonenberg>
but at the rate things are going it probably will not happen until after i get back from my wedding
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<pointfree>
cyrozap: the physical arrangement of I/O ports with respect to the DSI blocks makes less logical sense but it is consistent (for input, that is. Inputs are directly connected to a DSI block and their mapping to DSI's is not configured)
<pointfree>
that's the next picture to complete.
<pointfree>
I'm thinking a lot of the ports are associated with the analog array or various on-chip peripherals.
<pointfree>
That might also explain the gaps in numbering between the UDB banks and such.
<pointfree>
the bigger package will have more pins. doh!
<azonenberg>
:)
<azonenberg>
Would not surprise me if a lot of psoc dies are the same but missing bond pads
<azonenberg>
greenpak has at least one case where the same die is bonded out two different ways
<azonenberg>
same total pin count but you trade one GPIO for a vcc pin to get a separate i/o raio
<pointfree>
Yeah, I think that's the case with my CY8CKIT-059 (CY8C5888LTI-LP097) with regards to I/O. All PSoC 5LP's have 24 UDBs etc. Although there are different amounts of flash and ram across the PSoC 5LP family.
<azonenberg>
well flash/ram is probably different masks
<azonenberg>
because the only reason to have less ram is to save power
<azonenberg>
and die size (aka cost90
<azonenberg>
)*
<azonenberg>
the only reason to have less flash is to reduce die size (i guess it probably saves a little power too, but not as much since it doesnt leak like sram)