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<pointfree>
Marex: I know right, the flexibility of routing on FPGAs and CPLDs makes one see patterns that aren't there.
<pointfree>
...and usually are not there because there's little reason to have redundancy in the patterns for the sake of learnability.
<Marex>
pointfree: altera FPGAs are kinda linear , just pretty complex
<Marex>
pointfree: there are quite linear patterns too, one just has to discover them
<azonenberg_work>
It depends on the architecture
<azonenberg_work>
xilinx cplds for example do have somewhat limited routability
<azonenberg_work>
On that note
<azonenberg_work>
I am very interested in taking my old coolrunner code at some point
<azonenberg_work>
and making a libxbpar based place-and-route for it
<azonenberg_work>
I'm going to totally rewrite it, the old code was made before i fully understood how the device worked
<azonenberg_work>
now there's a few bits and pieces i dont have figured out, but the bulk is understood
<azonenberg_work>
So with a little more RE i should be good
<azonenberg_work>
Could probably black-box it in a weekend if i actually put the time into it
<azonenberg_work>
Time i don't have right now but hey, the overall project is still moving :p
<Marex>
azonenberg_work: oh hey, I pushed minor update to the doc/lab.txt
<Marex>
azonenberg_work: still not entirely public
<azonenberg_work>
:)
<azonenberg_work>
And sorry for being afk a bunch, things got crazy
<azonenberg_work>
i'm en route home from a funeral right now
<Marex>
azonenberg_work: I am working on it on and off, things are crazy here as well
<pointfree>
Cypress PSoCs have very well populated routing channels, but as the patent says, the routing works by short-circuiting. I've been thinking about expressing or simulating routes with short circuit evaluation like what you might find in an if-statement condition.
<azonenberg_work>
Interesting
<pointfree>
short-circuiting also happens to give even more connectivity
<azonenberg_work>
The routing in the coolrunners is an tristate (pass transistor based) shared bus for each output
<azonenberg_work>
with eight inputs for the 32a
<azonenberg_work>
Vdd, Vss, and six inputs chosen out of the 65 global PLA inputs
<azonenberg_work>
The selector code is one-hot
<azonenberg_work>
8 bits per output
<azonenberg_work>
For the greenpak, it's a dense-coded selector which means they probably have some kind of decode circuit in there (every input can route to every output)
<pointfree>
well, everyone does it differently
<azonenberg_work>
I have not yet looked at the greenpak to see how the decode is done
<azonenberg_work>
curious, thouh
<azonenberg_work>
Maybe if i get a chance this week i'll HF a 46620 down to implant and see what it looks like
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<pointfree>
I could consider the parallel segments as being an OR'd together set of arrays of in-series, AND'd together switches -- possibly finger on an idea for folding routing into the synthesis step.
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