11:24 <azonenberg> tnt: so i got the crc working and i didnt have to use the decomposition trick

11:25 <_whitenotifier-f> [starshipraider] azonenberg pushed 1 commit to master [+0/-2/±0] https://git.io/JkWrB

11:25 <_whitenotifier-f> [starshipraider] azonenberg 070e7bc - Removed redundant simulation for architecture that never got used

11:25 <azonenberg> a fully unrolled 128 bit implementation actually made timing, the only hard part was doing partial words

11:25 <azonenberg> i ended up using a pipelined design that contained 3 stages at the end

11:25 <azonenberg> 64 bit, 32 bit, and 0/8/16/24 bit variable width

11:26 <azonenberg> it's 877 LUT, 436 FF, and makes timing on a -2 kintex7

11:26 <tnt> azonenberg: oh nice.

11:26 <tnt> Do you know the max logic depth (in LUTs) ?

11:27 <azonenberg> my plan right now is to do all of my design work and timing signoff on a -2 speed

11:27 <azonenberg> but build the first two prototype maxwell boards with a -3

11:28 <azonenberg> so i have a bit of margin i can pull out if i run into problems later on

11:29 <azonenberg> The critical path right now is in the variable width crc, from the input data register through the crc logic and then a mux specifying whether we're using the variable width path at all or not

11:29 <azonenberg> Six levels... a lut2, a lut3, and four lut6s

11:29 <azonenberg> 767 ps logic, 2172ps routing

11:31 <tnt> damn, fpgas have gotten faste ;)

11:32 <azonenberg> So now i think i'm going to get back to the rx side of my 40G MAC and start building out the IP stack

11:32 <azonenberg> with a short detour later in the week to prep some boards for ordering

11:33 <azonenberg> well, supplies

11:33 <azonenberg> i'm ordering the production MEAD enclosures so i need to finalize the design, the prototype batch had problems where the screw holes weren't drilled deep enough

11:33 <azonenberg> they were drilled to spec but i hadnt specified enough depth for the length of my screws

11:33 <azonenberg> so i need to either find shorter screws or update the cad design to have deeper holes, or both

11:36 <azonenberg> then i also need to finalize the design of the new AKL-PT2 PCB with soldermask, as well as the mold for the silicone potting