00:25 <Degi> I kinda wonder how jlc manages to get 10% tolerance

00:25 <Degi> Do they order like random prepregs?

01:00 <azonenberg> Degi: no, that's probably because of metal density variations on your boards

01:00 <azonenberg> regions with no copper vs copper on all layers

01:00 <azonenberg> you can't really control for that at the fab level, if you need tighter thickness control you have to add dummy copper fill to inactive areas. Like CMP filler on ICs

01:12 <azonenberg> https://www.antikernel.net/temp/s21-match.png btw (file is named wrong, this is actually S11, but i'm too lazy to change it lol)

01:13 <azonenberg> latest simulation is much closer to reality. I think this is about as close as I will be able to get before upgrading my solver

01:43 <Degi> Neat

01:43 <Degi> Oh is CMP that stuff thats everywhere on unused IC areas

02:48 <azonenberg> To be precise, CMP is chemical-mechanical polishing, the process used to smooth out the wafer before the next layer is added, and remove excess metal after plating

02:48 <azonenberg> the filler is added to keep things flat because the polishing removes oxide and metal at slightly different rates due to varying hardness

02:49 <azonenberg> It's commonly called "CMP filler" because it aids the CMP process

23:12 <azonenberg> Status update... TCP stack is coming along nicely, been busy with some other stuff

23:13 <azonenberg> i have some errors in tx checksum calculation but am close to a minimum viable test platform, hopefully tonight

23:14 <azonenberg> I also just got a shipping confirmation from Multech. While the actual final-rev probe PCBs are still several weeks out, they were able to squeeze an inert FR4 dummy, routed to shape, into the schedule earlier

23:14 <azonenberg> So i'm going to use this as a test subject for some potential tweaks to the enclosure while i wait

23:14 <azonenberg> The mechanical dummy should be here Friday

23:30 <azonenberg> Also the crowdfunding campaign for the probes was approved. https://www.kickstarter.com/projects/azonenberg/akl-pt1-2-ghz-passive-oscilloscope-probe?ref=80pddj&token=ed31cda5 is my draft, any suggestions before it goes live?

23:37 <miek> i'd swap the first two photos. it makes more sense to me to have the finished product as the headline photo, and the PCB shot down with the tech data

23:38 <miek> a section with pics of the different kit options might be good too, to make it really clear what each one comes with

23:39 <azonenberg> I'm keeping the photos the way they are because i had enough trouble convincing kickstarter review staff that i had a prototype

23:40 <azonenberg> apparently VNA measurements didn't look like a prototype, i guess they wanted to see a board shot or something

23:40 <azonenberg> despite being far less useful at convincing an engineer of how mature the real product is

23:40 <miek> hah, fair enough

23:40 <azonenberg> my original top photo was a S21 plot

23:40 <azonenberg> and i only had the assembled prototype pic kinda buried in there because i didn't think it was super relevant

23:41 <azonenberg> I will be posting a photo of the final board rev mechanical mockup on friday when it comes in. Will probably go live around then

23:46 <azonenberg> miek: does the rest look sane? and do the packages/prices sound reasonable?

23:51 <miek> yeah, it all looks good to me