<azonenberg>
FINALLY my probe test boards have left shenzhen
<azonenberg>
They were mailed on the 8th
<azonenberg>
left sz on the 15th
<azonenberg>
maybe no flights for them to get on?
<Degi>
Weird
<azonenberg>
Back side of afe test is out of the oven and cooling off
<Degi>
Neat
<azonenberg>
i'm thinking to make the most realistic test i can, i'll hook the afe test's uart to the fpga tcp stack
<azonenberg>
then the tx side of the uart to the pc since my tcp stack can't transmit yet
<azonenberg>
but this will let me exercise as much of the system as i can
<azonenberg>
with an integralstick and some wires
<azonenberg>
i'm just kicking myself for not breaking out any of the fpga gpios on the hmcad test board
<azonenberg>
so when that comes in, i will probably bodge a wire onto it as a uart
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<bvernoux>
hello
<bvernoux>
so test Peak LCR45 with Tweezer option is nice
<bvernoux>
checked some capacitor COG 5% and the accuracy is nice
<bvernoux>
28pF advertised and measurement to 27pF
<bvernoux>
need to check high precision resistor to check the accuracy
<bvernoux>
just received my freezing spray which in theory can go down to -45°C ;)
<bvernoux>
will be great to test Crystal/TCXO/VCTCXO variance ....
<bvernoux>
also accuracy on Inductor is quite nice
<bvernoux>
checked vs my VNA measurement on small inductor < 900uH and it is quite stable and accurate
<bvernoux>
@200kHz of course
<bvernoux>
as it is impossible to measure such small inductor with freq < 100kHz
<azonenberg>
bvernoux: btw, for measuring probe input C
<azonenberg>
do you think the best option is to VNA it and derive C from the s2p?
<azonenberg>
i feel like a near-DC capacitance measurement won't be of much use
<azonenberg>
also probe characterization PCBs are in Alaska (that's a new path, never had a package routed through Anchorage before)
<azonenberg>
eta tomorrow
<azonenberg>
SMA torque wrench should be coming in today
<azonenberg>
So i did some back-of-the-envelope design calculations for MURDOCK
<azonenberg>
3840 Gbps of data coming off all the 32 AD9213s. One SODIMM of DDR4 2400 is 153 Gbps. So for bandwidth alone, I'd need a minimum of 25 channel memory
<azonenberg>
The most sane division of labor is probably one FPGA per channel card, with one channel of RAM dedicated to each ADC
<azonenberg>
So eight FPGAs, plus probably one more for top level synchronization/readback, and 32 sticks of ram
<electronic_eel>
I asked PMK about details for their tetris grabbers order no 899-000-000
<azonenberg>
and? any reply yet?
<electronic_eel>
they sent me a datasheet excerpt which I could identify as pomona 72906
<azonenberg>
yeah there are so many layers of reselling in the electronics industry that reverse engineering the supply chains and figuring out what you are *actually* buying can be quite hard
<electronic_eel>
they have a flexible nose, the ez-hooks don't have that. that might come in handy some time
<azonenberg>
but if you figure it out you can cut a lot of $$
<azonenberg>
They're also $13 each
<azonenberg>
at digikey
<electronic_eel>
pmk offered them for like 8$
<electronic_eel>
but when you talk to pomona directly I guess they will be cheaper than at digikey
<electronic_eel>
I think I will put one of those in my next order and try them out
<electronic_eel>
but I hoped it was some kind of replacement for a traditional scope hook, adapted for the tetris
<azonenberg>
i'd be iffy on using those beyond a few hundred MHz
<electronic_eel>
that would be shorter than the grabbers
<electronic_eel>
yes, exactly
<azonenberg>
ok i'm gonna go populate the front of the AFE board now
<electronic_eel>
nice, looking forward to some nice board bringup and measurement results
<azonenberg>
well full measurements will have to wait until the VNA comes in
<azonenberg>
Actually just got an email from my dealer with an expected ship date
<azonenberg>
the 27th
<electronic_eel>
yeah, but there are a lot of tests you can do without I think
<azonenberg>
of course
<electronic_eel>
hmm, seems like they don't have them on stock and order them directly from pico
<electronic_eel>
I guess VNAs in that price range don't have that high volume
<azonenberg>
when i placed the order, the dealer had ten units on order from pico
<azonenberg>
which hadnt arrived yet
<azonenberg>
i asked for a traceable cal which is non default, so they had to hold up the order by a bit and run a cal at pico's factory before sending one of the ten to me
<electronic_eel>
ah, so it is the cal that is not the common thing and they do that just on demand
<azonenberg>
yeah they do a non-traceable manufacturer cal by default
<azonenberg>
HMCAD1520 characterization board back from fab, shipping to me shortly
<azonenberg>
also apparently i am out of Keystone 5016 test points. I swear i had a hundred or so on cut tape sitting around
<azonenberg>
all i found was two
<Degi>
bvernoux re freezing spray: Lighter gas (the butane version) can cool a TO220 to -45 °C
<azonenberg>
Degi: that sounds... hazardous
<azonenberg>
So three of the ground test points on my AFE board won't have a handy clip soldered to them
<Degi>
Hm do we have something to prevent overloading the ADC with the last OP amp's output?
<azonenberg>
Yes
<azonenberg>
that's what the last stage schottkies are for
<azonenberg>
and the 1v8 clipping rail
<Degi>
Lol totally forgot about that
<Degi>
Huhh murdock will have 8 inputs? Will they be individually placeable?
<azonenberg>
what do you mean placeable?
<Degi>
Like that you can only have 1 input
<azonenberg>
Not interleavable
<azonenberg>
The proposed design is 32 ADCs on eight 1-channel cards
<azonenberg>
each card will probably have a virtex ultrascale+ or a couple of smaller fpgas
<azonenberg>
four sodimms of ddr4
<azonenberg>
and four adcs
<Degi>
I mean whether you can just have 1 channel instead of 8
<azonenberg>
There is no need to interleave more than that, because 40 Gsps is well over nyquist bandwidthOh
<azonenberg>
Yes
<azonenberg>
They will be individual cards plugging into a backplane of some sort
<monochroma>
euro rack!
<azonenberg>
monochroma: that is the plan
<azonenberg>
all of the bigger scopes will be eurorack based
<Degi>
Also why 8?
<azonenberg>
8 is a reasonable number to fit on a scope. 4 is often not enough
<Degi>
(Like most standard scopes have 2 or 4 but we could have like 20 slots or so
<Degi>
)
<azonenberg>
more than 8 and you start hitting mechanical limits
<azonenberg>
front panel space etc
<Degi>
Hm ok
<azonenberg>
but we could possibly scale further, TBD
<azonenberg>
for a 1U, it's limited by front panel space
<azonenberg>
with taller scopes more might be viable
<Degi>
Hm theres 1U eurocard
<azonenberg>
but then you start hitting backplane limits on bandwidth etc
<azonenberg>
The subracks i have now are for 3U x 160 mm deep cards
<azonenberg>
If possible, i would like to fit ZENNECK into one of those
<azonenberg>
DUDDELL might be doable in 1U if we do long deep analog boards, but ZENNECK will probably need more pcb space than we can easily fit in 1U
<azonenberg>
so i plan on having it be 3U x 160 mm form factor with one small fpga per channel for buffering data off the four ADCs, then maybe a power supply card
<azonenberg>
and a fpga/cpu card
<azonenberg>
then a passive backplane
<Degi>
Hm
<Degi>
For zenneck we could have some cheap 20 € FPGA on each card and maybe a stick of RAM
<azonenberg>
yes that is the idea. That might be a good use case for ecp5 if the specs fit right
<azonenberg>
Have one 5g link from each card to the master fpga
<Degi>
Hm I will try later how good it works with the HMCAD (but I am pretty sure it does...)
<azonenberg>
then 10g from the master to the outside world
<azonenberg>
or 40g if we pick an fpga with enough transceivers
<Degi>
Hm depending on what the master is... maybe 2x or 4x 5G... But we cant do live streaming anyways because we have 32 Gb/s of input and 4x 5G is 20 Gb/s if we dont use 8b10b (lol)
<monochroma>
hehe multiple bonded 10g links across FPGAs for 40G ;)
<Degi>
Hmm, not sure if we should not do 40 G, that thing probably costs a bunch anyways, I guess a 40 G wont do harm lol
<Degi>
Can we have a 40 G on each channel
<Degi>
Maybe with 64/66b coding on the 40 G side we could do live streaming to a SAN or so
<Degi>
Also uhm when you have the test board can you qualify the HMCAD to 650 MHz? That way we can see how the rolloff looks like
<azonenberg>
40G is actually not that expensive
<azonenberg>
40Gbase-SR4 QSFP+s can be found on FS for $39
<azonenberg>
and that can be easily broken out into four 10G lanes, although we might need a bitstream change to support it (not sure how easy runtime switching of 10G/40G will be)
<azonenberg>
QSFP+s use four 10G lanes, and 40Gbase-SR4 is literally four 10G lanes bonded together
<Degi>
I mean you can theoretically stick a FPGA mux into the frequency generator path
<azonenberg>
no it's the same frequency
<azonenberg>
thats the point
<azonenberg>
So if we put a 40g port on there with an adapter cable you can easily pull out one 10g link and run the phy at 10g
<Degi>
Ah
<azonenberg>
in fact initial firmware will only use lane 0 of the qsfp and run at 10g
<Degi>
It would be really cool to have a ZENNECK channel on a 40 G lol but kinda unnecessary
<azonenberg>
40g will come later
<azonenberg>
but basically the way i see it is, if we have the transceivers on the fpga we should pin them out
<azonenberg>
we can always not use them
<azonenberg>
in fact, depending on exactly how many pins the FPGA on BLONDEL uses i might put dual 10G on it
<azonenberg>
e.g. one direct to a workstation and one to a switch
<azonenberg>
because the tlk10232 has two ports, and if we need to use an fpga with eight GTPs
<azonenberg>
why not bond out the other one?
<azonenberg>
the cost is a tiny bit of pcb area for a few diffpairs, a handful of passives, and one more connector
<Degi>
Hm yeah
<Degi>
Hm how much sample depth do we wanna have? I think at least 4 GS/channel would be nice
<azonenberg>
BLONDEL will have a single DDR3 SODIMM, i plan to populate the initial prototype with 4 GB. At 12-bit resolution that's 2.66 gigasamples, at 8-bit that's 4 gigasamples. shared across all channels
<azonenberg>
So if we had two 12-bit analog plus two 8-bit digital channels , that's 40 bits of data per sample which is 800M samples. Or 200M samples per GB of RAM
<azonenberg>
It looks like DDR3 SODIMMs are available up to 16 GB per module
<azonenberg>
Which would give us 3.2 GS with all channels enabled at max resolution, and correspondingly more if we only use some channels or run the analog channels in 8-bit mode
<electronic_eel>
I keep thinking about a way to easily probe small bare wires with the passive probe
<electronic_eel>
the grabbers are too long and add inductance
<electronic_eel>
but how about this: ED10474-ND
<electronic_eel>
it is like the receptable on the probe, just for much smaller diameters
<electronic_eel>
the od is 0.71mm, so it should fit into the receptable of the probe
<electronic_eel>
and then you can push in wires 0.2 to 0.33mm
<azonenberg>
interesting
<azonenberg>
that would work i think
<electronic_eel>
only thing that might be a problem is the length: it is just 1.63mm long, don't know if the receptable on the probe will grab it properly
<electronic_eel>
the alternative would be ED5062-ND
<electronic_eel>
that has a longer tail that should go into the receptable on the probe (so it doesn't fall in)
<electronic_eel>
I think I'll add these parts to my next order and try them out
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<Degi>
Hm I think we should at least have an option for ~ 1 s of sample memory. 4 GB is enough for 2 seconds with 8 inputs
<Degi>
On ZENNECK we'd need like 4 GB per channel, so 32 GB total
<Degi>
Will scopes other than BLONDEL have a LA?
<azonenberg>
Yes
<azonenberg>
at least BLONDEL and DUDDELL will have connections for the CONWAY LA. Probably ZENNECK too
<azonenberg>
VOLLUM and MURDOCK may support CONWAY as well, but will also have the option of mounting a 12.5 Gsps SERDES-based LA
<sorear>
is CONWAY new
<azonenberg>
sorear: CONWAY is the 8-bit LA pod
<azonenberg>
Which has its own name because it will be used with multiple generations of scope
<monochroma>
stand alone!
<azonenberg>
AFE board is out of the oven and cooling off
<azonenberg>
still have to put a few connectors on by hand
<azonenberg>
Right about now i'm wishing i had a function generator to test it with lol
<bvernoux>
azonenberg, I saw the answer of PicoScope Team about the VNA support on Linux
<bvernoux>
azonenberg, It seems you will need to use a PC with Windoz
<azonenberg>
yeah i have a windows VM on this b
<azonenberg>
on this box
<azonenberg>
so i'll just use that
<azonenberg>
annoying, but what i expected
<bvernoux>
humm VM probably not the best for USB 3.0
<bvernoux>
as it is USB 3.0 IIRC
<bvernoux>
anyway to retrieve SxP it does not requires USB 3.0 ...
<bvernoux>
files are something like 1MB in worst case if you use 10Kpoints ;)
<bvernoux>
about 30KB with 1601pts S2P file
<electronic_eel>
depends on how they implemented it
<electronic_eel>
if most of the processing is done on the pc, it could be substantially more data
<bvernoux>
the point is for a VNA it is not required to have ultra fast USB
<bvernoux>
USB 2.0 HS is enough
<bvernoux>
electronic_eel, there is pretty nothing even if all is done on PC
<bvernoux>
even if using RAW 64bits for each point ;)
<bvernoux>
using Double64
<azonenberg>
sure but what if it's a SDR?
<bvernoux>
electronic_eel, I see on my old HP raw data are even more compact
<azonenberg>
and streams raw i/q over usb
<bvernoux>
I really doubt it can be used like an SDR ;)
<azonenberg>
all kinds of ways a sloppy design could use lots of bw, i mean
<bvernoux>
not even like a Spectrum Analyzer
<electronic_eel>
but if it is not one point, but a whole bunch of sampled datastream, that later gets calculated into one point?
<bvernoux>
as it is clearly not the use case but who know ;)
<bvernoux>
electronic_eel, it is clearly not like an SDR ;)
<electronic_eel>
the output you get from the software not, but you don't know about the implementation until teardown/wireshark
<bvernoux>
but yes hardware behind have probably great features but I doubt it can be "hacked" like an SDR/SA ;)
<bvernoux>
will be interesting to check
<bvernoux>
I do not know if they provide access to low level over USB ;)
<bvernoux>
my HP is amazing for that as everything is documented even raw data format ;)
<bvernoux>
it is why I drive it from my PC with my own QtApp over USB to GPIB ;)
<bvernoux>
amazing for a VNA from 1990 ;)
<bvernoux>
but too loud, heavy and slow vs PicoVNA ;)
<bvernoux>
and also half of the price ;)
<azonenberg>
bvernoux: well depending on when in the year it was made
<azonenberg>
your VNA might be older than me :p
<bvernoux>
azonenberg, hehe good question it is wrote on the back ;)
<bvernoux>
Copyright 1986-1997 ;) and Firmware HP8753D.06.14: Oct 27, 1997 (it was the last version)
<bvernoux>
The things not fun is when I want to use my own SMA calibration from my Calibration Kit for S2P
<Degi>
Huh JLC is doing PCB + assembly for under 2 €
<bvernoux>
I cannot set it to 1601pts as when I want to calibrate it say not enough memory ;)
<bvernoux>
for 2 ports calibration ;)
<Degi>
lol
<bvernoux>
IIRC it is not possible to add more RAM ;)
<bvernoux>
it is already the biggest version
<bvernoux>
there is huge 512KB non volatile memory ;)
<bvernoux>
Anyway big respect for those ultra old HW as it is rock solid I doubt we can find anything(electronic) today which can last more than 30years ;)
<bvernoux>
Also it comes with fully detailed schematics bought for 20euros ;)
<Degi>
I mean if you dont cheap out too much on components, that should be possible
<Degi>
Like this > 20 year old scope here had all SMD electrolytics leaked when I got it, since then they have gotten much better in quality
<Degi>
I mean you get what you pay for
<Degi>
Like polymer caps aren't gonna dry out
<azonenberg>
Yeah i almost never use electrolytics
<Degi>
Is there a reason for no solder mask on the traces?
<azonenberg>
Lower loss, but more importantly for my purposes it simplifies impedance calculations
<Degi>
Ooh thats the test point on the square pads
<azonenberg>
yeah. but i only had two
<azonenberg>
i just ordered more but for now the rest have no clips
<Degi>
Hmm, maybe I should've done that too for the PCIe device lol... I hope the solder mask doesnt affect too much
<azonenberg>
those are all ground references
<Degi>
Bottom middle is the processor, right?
<azonenberg>
anyway modeling soldermask effects on impedance in sonnet light is annoying because it basically requires you add another dielectric layer of mask above your traces, then air above that
<azonenberg>
which, when you only have two layers in the basic edition, makes it difficult to also model effects of ground plane cutouts etc
<Degi>
oof
<Degi>
Is the basic version free?
<azonenberg>
if i'm doing stuff that's fast/sensitive enough for a little change in impedance to matter, i prefer unmasked for that reason already
<azonenberg>
No, lite is free
<azonenberg>
L2 basic is around 4000 USD
<Degi>
oof
<azonenberg>
L2 Silver adds a larger cap on design size, L3 Gold is around 12 kUSD and ups the layer count to 3
<azonenberg>
Professional removes all limits and is somewhere around 25 kUSD
<azonenberg>
It's a nice tool. but not cheap
<azonenberg>
and yes bottom center is the mcu
<azonenberg>
bottom left is the dac, center is the VGA
<azonenberg>
Anyway will be testing / starting firmware dev this evening or tomorrow. Have a bunch of stuff to do for $dayjob, then a backup server to build and set up
<Degi>
Lol... Kinda funny how there's voltage regulators everywhere
<azonenberg>
and i have to move a bench in my lab out of the way because i have HVAC guys coming tomorrow to put in cooling so the lab doesn't melt when it gets a bit warmer outside
<azonenberg>
Yeah i just crammed them in wherever they fit
<azonenberg>
The actual production board will be a bit nicer layout because i won't be dodging SMA outputs and test points as much
<azonenberg>
And it will be designed to have EMI cans over the AFEs
<azonenberg>
also i have a lot of strap resistors on signals for easier reworkability if i set them wrong, the real board will just have vias to power/ground
<Degi>
Hm maybe for future boards, the resistors besides TP6/7 should be put on the input side of the OP amp to minimize capacitance effects
<Degi>
On the other hand that could cause oscillations idk
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<Degi>
The inductors look cute
<Degi>
Is C2 between L2 and L3 supposed to be DNP?
<azonenberg>
No. I forgot it when assembling the board, noticed right after taking the picture, and populated it
<azonenberg>
good eye
<Degi>
Heh
<azonenberg>
soldering around the relay was tricky
<azonenberg>
tight quarters
<Degi>
"The square wave looks weird"
<Degi>
How meltey is the relay casing? Would a soldering iron damage it?
<azonenberg>
Momentary contact didn't seem to do any damage
<azonenberg>
but i didn't want to find out
<Degi>
Nice, good relay
<Degi>
On the final version there should be some cool silkscreen, like dividing it by functional area etc
<Degi>
Heh the ADL5205 seems to be rather easy to use as long as you dont want to read... Just send 8 bits heh