<monochroma>
azonenberg: FYI Vitesse was bought by micro semi, and then micro semi was bought by Microchip, so most of their parts are available on digikey with open datasheets
<monochroma>
though last i looked microchip was wanting to sell you software for the higher end switch engines
<azonenberg>
monochroma: I don't believe in corporate redemption at this point :p
<azonenberg>
if broadcom got bought by a more open company i still wouldn't buy their parts
<monochroma>
(which sorta happened, broadcom got bought by avago, and avago renamed to broadcom. and now lots of broadcom chips are on digikey :P but yeah broadcom still sucks)
<azonenberg>
also ooh just got tracking from digikey for a package
<azonenberg>
Don't know which one, but i hope it's the 75R resistors
<azonenberg>
electronic_eel: Just ordered one of the Hammond enclosures and the Matrix LCDs I am planning to use for BLONDEL. Should help when doing paper sketch fit testing of various connectors and such
<azonenberg>
i want to be able to print out a 1:1 replica of the proposed front panel and see how it "feels"
<azonenberg>
Hmmm
<azonenberg>
maybe we should use SFF 8087 as the scope connector
<azonenberg>
it appears that sidebands are not supported by the 8088 connector
<monochroma>
oh?
<azonenberg>
the 8088 connector is only 26 positions
<azonenberg>
the 8087 is 36
<azonenberg>
they remove one pair of grounds and the sidebands
<azonenberg>
So that cable i just ordered is useless :p
<azonenberg>
good thing it was only $15
<monochroma>
clearly you should go with SFF-8470
<monochroma>
(not because i think it's an awesome looking connector or anything. 100% purely for technical reasons. yes.)
<azonenberg>
lol
<azonenberg>
i mean i guess we could just put a slightly larger cutout in the scope front panel for the 8087 locking latch
<azonenberg>
Wouldn't be the end of the world
<monochroma>
8470 is usually pretty expensive and usually uses thumb screw hold downs
<monochroma>
well
<monochroma>
can use thumb screw
<monochroma>
i think my infiniband cards are all thumb screw
<azonenberg>
somewhat simplified mockup of the enclosure and front panel, not including ext trigger, LA, active probe connections, boards, rear panel, etc
<monochroma>
:O
<azonenberg>
if i wanted to be more exact i'd need to work off the actual step model of the enclosure from hammond and kicad exports of the actual board designs
<azonenberg>
but at this stage in the design we don't need that
<azonenberg>
Regarding board structure, at this point i am picturing five boards total
<azonenberg>
there will be a UI board behind the LCD with a STM32 that may also perform various system monitoring functions etc
<azonenberg>
Two ADC+AFE boards behind the SMAs
<azonenberg>
a mostly-passive adapter board going from the ext trig and LA connectors back to the FPGA board, may literally just be a SFF-8087 + SMA -> q-strip
<azonenberg>
then the FPGA board in the back
<azonenberg>
Sound reasonable?
<azonenberg>
Probably QTHs on all of the upper level boards and QSHs on the FPGA board, exact pin count of each interface TBD
<monochroma>
hmmm i would probably do edge launch card edge connectors from the ADC+AFE PCBs to the FPGA board, basically make the FPGA board like a backplane
<azonenberg>
mating that seems like it would be challenging
<azonenberg>
and i really dont want to use something huge like pcie
<azonenberg>
we'd need like an x16 for everything
<azonenberg>
it wouldnt even fit
<monochroma>
ahh
<azonenberg>
I'm drawing up an interface design document now
<azonenberg>
figuring out what signals each board needs to the others
<monochroma>
so if you are going to do say
<monochroma>
have the AFE+ADC boards overhang the FPGA board with q-strips, i would def put some mechanical hold downs through the FPGA PCB around the q-strip then
<monochroma>
just standoffs to screw into
<azonenberg>
Yeah we'll figure out specifics once we know rough board dimensions etc
<azonenberg>
one thing i have to work out is how the standoffs will mate to the hammond enclosure
<azonenberg>
most likely i think is to drill holes then tap them
<monochroma>
yeah
<monochroma>
might be a bit annoying to get flush
<azonenberg>
the hammond engineering drawings on digikey do not seem to specify the metal thickness clearly
<azonenberg>
i ordered one so i can measure
carl0s has quit [Remote host closed the connection]
<azonenberg>
So it looks like if i don't put any IO expanders or level shifting, except when necessary to interface with 5V logic, on the analog board
<azonenberg>
and i keep spi buses point to point for signal integrity
<azonenberg>
one analog board needs 12 lanes of LVDS, 41 of LVCMOS33, and 5 of LVCMOS18 to the FPGA board. Which comes out to 70 pins plus power/ground
<azonenberg>
A QTH-060 has 120 pins, keeping a 2:1 data to VCCIO ratio and ground on the center requires ~105 pins, which leaves us plenty for +12V system power
<_whitenotifier-3>
[starshipraider] azonenberg pushed 2 commits to master [+11/-10/±0] https://git.io/JvNX3
<_whitenotifier-3>
[starshipraider] azonenberg 5d75d40 - Moved LA pod design to CONWAY subdirectory
<azonenberg>
So i just finished preliminary interface design and I/O budgeting
<azonenberg>
We're looking at a 100 mil header for the UI board, a QTH-030 for the LA/trigger board, and a QTH-060 for each of the two acquisition boards
<azonenberg>
A total of 317 I/Os: 32 lanes of LVDS, 107x LVCMOS33, 25x LVCMOS18, and 121x SSTL
<azonenberg>
one sodimm of DDR3L 800
<azonenberg>
with at least 64% bus efficiency required to keep up with 16 Gbps of LA and 16 Gbps of ADC data
<azonenberg>
This adds up to 2 banks of LVDS, 2 of LVCMOS33 plus 7 extra pins we can level shift to less heavily loaded banks, 1 of LVCMOS18, and 3 of SSTL
<azonenberg>
Whiiich means we're looking at the XC7A200T in FBG676 package
<azonenberg>
With about 80% of the I/Os utilized. Possibly more, since i didn't account for such niceties as boot flash in this budgeting
<azonenberg>
now, most of the LVCMOS33 is fairly slow SPI buses. So it's possible we could cut down to a FGG676 XC7A75/100T, then add a second small/cheap fpga for io expansion to run all of the various buses to the dacs etc
<azonenberg>
Another possibility is to put a q-strip back on the UI board, and have that stm32 run some of the lower speed control stuff on its own
<azonenberg>
perhaps even have the control plane socket terminate on the STM32, while the data plane socket runs to the FPGA
<azonenberg>
the STM32 only has 100 Mbps ethernet but that's more than sufficient for control plane
<azonenberg>
At which point that would become a UI/processor board
<azonenberg>
I think if we do that we can easily fit in the smaller fpga
<azonenberg>
The 7a75t/100t have six io banks, 300 pins total. If we use three banks for SSTL, two for LVDS, we can put the last at LVCMOS33. Use it for boot flash, RGMII to the gigabit PHY (which is both 1.8 and 3.3 capable but my original concept called for 1.8), and RMII to the STM32
<azonenberg>
monochroma, lain: thoughts?
<azonenberg>
(also how many banks did you use for the ddr3 sodimm on your board - 3?)
<azonenberg>
We can also think about merging some of the SPI and omitting probably-not-necessary signals like spi data output from the dac
<azonenberg>
I also assumed separate i2c buses for a lot of sensors scattered around, if we make proper use of address pins i suspect we can cut those in half easily
<azonenberg>
e.g. the main board, LA board, and CPU board can likely share one i2c channel
<azonenberg>
oh, another benefit of doing it this way is that some stm32 gpios are 5V tolerant, so i can probably eliminate a fair number of level shifters
<azonenberg>
We can probably also reuse a lot of the software i'll be writing for the AFE test board this way, rather than having to rewrite it for FPGA
<Degi>
Hmm theres serdes io expander ICs which can send like 24 IOs over 2 pins
<azonenberg>
Degi: i mean there's lots of i2c etc io expanders too
<azonenberg>
my point is more, we're going to want a MCU for running the display anyway
<Degi>
Was there any discussion between "and i really dont want to use something huge like pcie" and "global ocean anoxic event" sounds like an airborne toxic event cover band"?
<Degi>
Ah yes
<azonenberg>
I don't want to make the mistake most other scope vendors do, putting performance critical waveform processing in software that becomes a bottleneck
<azonenberg>
That has to remain FPGA straight to DDR3 and then out gig-e
<azonenberg>
But if we can offload a lot of the slow control plane stuff like gain/offset configuration to software, that will free up pins on the FPGA
<azonenberg>
My proposal is to put a sort of ethernet switch in the FPGA. All transmit data from either MCU or FPGA logic gets sent out the single gigabit link to the host
<azonenberg>
Receive data is filtered: TCP goes to the MCU, anything else to the FPGA
<azonenberg>
they share one ip and mac address
<Degi>
The FPGA gets UDP?
<azonenberg>
Yeah. Because all waveform data will be UDP
<azonenberg>
i may not actually have any udp RX
<Degi>
Hm okay
<azonenberg>
it may be a transmit-only stream
<azonenberg>
use the TCP connection to say what port/ip you want data sent to
<azonenberg>
then start spamming waveforms
<azonenberg>
Down the road we'll want to do switching based on port numbers because i think i will eventually want waveform data to be TCP too
<azonenberg>
in order to allow flow control when on slower pipes
<azonenberg>
I may actually just implement an fpga tcp stack while i'm waiting for boards to come back - that would probably be the safest option since i need one for other projects anyway
<azonenberg>
anyway details TBD
<azonenberg>
the point is, the mcu will handle control plane while the fpga handles data plane
<azonenberg>
also, if we want to, for a relatively low cost we could add 10GbE to the board
<Degi>
Hm does the FPGA have 10 Gbit serdes, right
<azonenberg>
No it has 6G. But TLK10232s are cheap
<azonenberg>
We could slap one down on the board for relatively little as an optional addon
<Degi>
Hm yes just put the traces on the PCB and DNP it
<azonenberg>
Exactly
<azonenberg>
because otherwise all those serdes lanes are going to waste
<azonenberg>
which seems like a shame :p
<Degi>
Hm is there a serdes less version of that fpga?
<Degi>
Which specific fpga IC are we targeting anyways?
<azonenberg>
Artix-7. Tentatively the 100T in FGG676
<Degi>
Ah I see further up in the chat
<Degi>
Huh thats a pricy fpga
<Degi>
Hmh neat 740 MHz accumulator and multiplier
<azonenberg>
i mean, this is going to be a pricey scope. I'm not cutting corners
<azonenberg>
32 lanes of LVDS plus a DDR3 SODIMM will need a lot of FPGA
<Degi>
Hmm
<azonenberg>
oh and that doesn't include the trigger out pin and a few other things too
electronic_eel has quit [Ping timeout: 265 seconds]
electronic_eel has joined #scopehal
<azonenberg>
On a related note, the 8x HMCAD1520 scope will need an even beefier FPGA. You're looking at 88 lanes of LVDS for all of the ADCs, which comes out to 176 pins or four 7-series IO banks just for the waveform data
<azonenberg>
And 64 Gbps of waveform data, which probably means TWO sodimms of ddr3
<Degi>
Hm I guess the scope will have some decent sample depth?
<azonenberg>
At that point you're looking at a full xc7a200t in ffg1156. or alternatively, a multi fpga design
<azonenberg>
I guess going to Kintex for that could be an option too... let me think
<Degi>
Hm just hook up a FPGA for like 10 bucks to each ADC with a chip of RAM?
<azonenberg>
loose dram chips are $$$$ espeically in low volume
<Degi>
Oh
<azonenberg>
$20+ per chip for ddr3
<Degi>
Oof damn
<azonenberg>
you can get an entire sodimm for that much
<azonenberg>
Hence why i'm doing that
<Degi>
Hm make each FPGA control a part of the SODIMM? Is that possible at all?
<azonenberg>
No
<azonenberg>
they share common address lines
<azonenberg>
So... DUDDELL needs 64 Gbps of bandwidth for the ADCs, plus 16 for the LA, plus probably 10 for 10GbE to the host system is 82 Gbps if memory serves me right. 72 if we're ok with not being able to trigger while downloading a waveform, which i'd prefer to avoid
<azonenberg>
We'd be using a -2 speed FPGA, and a 4:1 memory controller on kintex7 can do 1866 MT/s on DDR3 or 1600 on DDR3L
<Famine>
do SODIMMs do any power management / bring up, or do you still need to do the bring up ?
<azonenberg>
Which comes out to 119 or 102 Gbps before refresh overheads
<azonenberg>
So if we use a kintex, we can get away with a single sodimm, not two
<azonenberg>
At which point we only need 7 io banks if we stretch things a bit. So we could use the xc7k160t in ffg676
<Degi>
Hm I think the ECP5 in the 756 BGA has 194 diff pairs and is waay cheaper... but they can't do more than 5 Gb/s in terms of SERDES which kinda limits ethernet conenctivity...
<azonenberg>
(fbg676 is much cheaper but not rated for 10G I/O)
<azonenberg>
can ecp5 even do 1gbps lvds?
<Degi>
Hm I tested it to 1.5
<Degi>
Not sure if it cant do more or whether the PLL gets too jittery when running at 1x division and 800 MHz...
<Degi>
1 Gb/s seems to work over those arduino cables in twisted pairs but I should do more testing
<azonenberg>
also ecp5 maxes out at DDR3 800
<Degi>
Hm yeh thats kinda a downside. Maybe a bit higher would be possible but I won't go over 1000, the bit error rate may increase
<azonenberg>
I'm not rigol, we arent overclocking things in these scopes
<Degi>
Okay
<Famine>
hrm speaking of jitter PLLs i should order some new caps for this rigol
<Famine>
jittery *
<azonenberg>
anyway, so tentative thought is to use xc7a100t-2fgg484c for BLONDEL and xc7k160t-2ffg676c for DUDDELL
<Degi>
I mean the fabric seems to do fine with more than 100% overclock depending on your circuit, as long as things happening in 1 cycle are short enough
<azonenberg>
fgg676* for BLONDEL sorry
<Degi>
Huh that FPGA looks like those old CPUs which didnt have a metal cover
<Famine>
azonenberg, how dare you insult rigol, they worked very very hard to make the ds1054z the giant heap of crap it is :P
<azonenberg>
Famine: lol
* azonenberg
is watching a signalpath video on lecroy's labmaster 10. The 100 GHz oscilloscope
<azonenberg>
now that is a work of art
<Degi>
I like how that name is so not cryptic compared to like "ds1054z"
<azonenberg>
Famine: sodimms are basically eight 8-bit dram chips with address lines ganged together
<azonenberg>
and an eeprom storing some metadata about max clock speed etc
<Degi>
Huh rigol oscilloscopes sold as "(Home Improvement Product)" lol
<Famine>
azonenberg, gotcha, so you still have all the fun of power management and bring up
<azonenberg>
yeah. But i will probably just use the xilinx IP for that
<azonenberg>
i'm not in the mood to reverse engineer the hard IP for the ddr3 phy right now
<azonenberg>
lain was looking into it a while ago but afaik she didnt get anything usable yet
<azonenberg>
yeah except i really dont want to deal with migen for the time being
<azonenberg>
anyway so i think that's basically the high level plan. Bump the mcu up from like a stm32f4 up to a f7, lcd interface to the front panel, RMII interface to the FPGA, and a bunch of spi/i2c to all of the dacs etc
<azonenberg>
the other option would be to load up to a bigger FPGA and nix the mcu entirely
<azonenberg>
but that will likely cost a fair bit more
<Famine>
bleh i think i'm at the point where i need to wind my own transformer
<Degi>
For what?
<Famine>
Degi, laser power supply
<Degi>
Heh neat
<Degi>
An ion laser?
<Famine>
808nm array
<Degi>
Nice
<Degi>
I wanted to get one of those a while ago but decided against it because I'd probably never finish it
<azonenberg>
ooook so i guess the question now is, where to go wrt priorities on the project now
<azonenberg>
Given that CONWAY is on hold until electronic_eel helps me figure out io protection, and once i order the board i'll probably be on hold until all of the other boards come in
<azonenberg>
I guess one thing i could do is work on the fpga tcp stack?
<Degi>
Hm maybe on the thing where the ADC is configured and samples are stored? Then it could be tested when it arrives
<azonenberg>
The ADC config code will be running on a stm32f0 i don't have a devkit for handy
<azonenberg>
to start it'll just be a handful of spi register writes
<Degi>
Hm yes
<Degi>
Quite a handful
<azonenberg>
actually wait no, the adc test board is going to the FPGA on integralstick
<azonenberg>
So i'll probably just slap a spi controller core down there and replay a hardcoded sequence of reg writes for setup
<azonenberg>
but i'll need the tcp stack to get waveform data off
<Degi>
Or an UART
electronic_eel has quit [Ping timeout: 256 seconds]
electronic_eel has joined #scopehal
<azonenberg>
yeah but if i have the tcp code i can try to write something resembling the actual system design
<azonenberg>
although i will have to store waveform data in block ram because integralstick doesn't have ddr on it
<Degi>
Yes that's a good plan
<azonenberg>
But it will be a good proof of concept
<Degi>
I mean it has a few Mb of that right?
<azonenberg>
integralstick can have any artix7 in ftg256. I'll probably use one that i loaded out with a 100t, the same die i will use on the real board. just a lower pin count package that do
<azonenberg>
that doesn't fan out the serdes, or many of the ios
<azonenberg>
it also has a stm32f777, the same mcu i plan to use on the processor / ui board
<azonenberg>
connected via RMII and a spi bus
<azonenberg>
we can replicate most of the control plane logic of the scope on this platform, i think
<azonenberg>
in fact, i think i have a spi bus from the mcu to the fpga
<azonenberg>
if i proxy that bus through fpga gpios, i can use the stm32 to configure the adc
<azonenberg>
and use the same actual adc config code i'll have on the real board
<Degi>
Now you have a stm32f0 devkit hehe
<azonenberg>
No its a f7
<Degi>
Hm right
<Degi>
Oh what about that one weird IC with bidirectional SPI
<azonenberg>
i was mixing the boards up
<azonenberg>
The f0 is on the afe board
<azonenberg>
THAT code will later have to be ported to f7, which should be easy
<azonenberg>
anyway so i think we have a plan
<azonenberg>
priority is now getting tcp on integralstick working
<azonenberg>
before hardware comes back from fab
<azonenberg>
The current stack uses a 32-bit datapath and runs at up to maybe 150 MHz (i haven't tested in faster speed grade FPGAs yet)
<Degi>
Heh
<azonenberg>
So i probably won't be able to saturate 10GbE with it, although i should easily be able to run at several Gbps. Meaning putting 10G on the board will provide a benefit, even if i can't saturate it without optimizing the stack more
<azonenberg>
This should be fine because DUDDELL will use a kintex7 that is a lot faster, and has native 10G serdes
<azonenberg>
actually, if i really wanted, i could probably put 40G on that board :p
<azonenberg>
but i feel like that is overkill for a scope in that performance class
<azonenberg>
I also don't think i will have the ram bandwidth to read data that fast while also capturing waveforms
<azonenberg>
BRAUN will likely have a similar bandwidth requirement to DUDDELL, 2x 5 Gsps ADCs instead of 8x 1. So very slightly more data, but not hugely
<azonenberg>
So i will probably use almost the same FPGA/ram subsystem on that
<Degi>
Does the fpga have enough serdes for the adcs=
<azonenberg>
None of those are serdes based
<azonenberg>
iirc the lm97600 is just a bunvch of fast lvds
<azonenberg>
let me double check
<Degi>
Hm yes 10 lanes output, probably 500 MB/s per lane I guess
<azonenberg>
yeah it's 10 lanes 8b10b coded
<azonenberg>
40 Gbps raw output, 50 Gbps after 8b10b coded, so...
<Degi>
Yes so 5 Gb/s raw per lane
<azonenberg>
ok yeah that will need serdes then
<Degi>
That sounds like a very fast lvds lol
<azonenberg>
Hmmm
<azonenberg>
I could do an xc7a200t in ffg1156 for that perhaps? it has 16x 6G serdes
<Degi>
Neat
<azonenberg>
hypothetical architecture: one 7a200t for each ADC, ten lanes to the attached ADC
<azonenberg>
six lanes free
<azonenberg>
use two lanes to connect the two fpgas
<Degi>
Hmh?
<azonenberg>
then the other four on one, designated master, to talk to a tlk10232
<Degi>
You have 40 Gb/s of data
<Degi>
You'd need at least 7 SERDES without 8b10b and like 9 with 8b10b
<azonenberg>
no
<azonenberg>
this isn't full realtime streaming
<Degi>
Ah right
<azonenberg>
each fpga has its own attached buffer ram
<Degi>
Well in that case that should suffice
<azonenberg>
1-2 sodimms per fpga of capture memory
<azonenberg>
then 2x 6G from slave to master fpga
<azonenberg>
and 4x 2.5G = 10G from master to PC
<Degi>
Hm 10G SFP+ transceiver right?
<azonenberg>
Yes
<azonenberg>
ZENNECK, with one LM97600 times 8 channels, will be a beast of a scope to design
<Degi>
Hm each channel will have 1-2 SODIMMs?
<azonenberg>
at that point you're looking at buffering 320 Gbps of data
<Degi>
Neat
<azonenberg>
you might be looking at an fpga dedicated to each ADC there
<azonenberg>
the other option would be to switch to MUCH nicer fpgas
<Degi>
Hmm also for the highest end scope maybe we could use RF mixers to extend the frequency range
<Degi>
Ah yes the 60k per piece FPGAs
<azonenberg>
well maybe not quite that much
<azonenberg>
but 5-10k per piece fpgas
<azonenberg>
a $293 @ qty 1 fpga per channel is likely far more cost effective in that scenario
<Degi>
Those things with 2.8 M logic elements lol
<azonenberg>
Oh, i have two VCU118s in my lab from a customer's project
<azonenberg>
you want big fpgas, those are big fpgas :p
<azonenberg>
xcvu9p
<Degi>
Like XCVU47P-3FSVH2892E is 100k on digikey
<azonenberg>
oh, i guess they get bigger now? the xcvu9p is only 50 kUSD on digikey
<Degi>
Huh cheapest of that is 30k lol
<azonenberg>
interestingly, the devkit is only about 7 kUSD
<Degi>
Huh?
<azonenberg>
the vcu118 has an xcvu9p on it
<azonenberg>
and sells for less on digikey than a single xcvu9p bare fpga
<azonenberg>
meaning when digikey sells those bare chips, they (and xilinx) are taking a massive profit
<Degi>
Huh xcvu9p has like 300 Mb of ram
<Degi>
Maybe they sell the devkit at a massive loss?
<azonenberg>
unlikely, i think it's a lot more likely that they sell the devkit at cost, give or take a bit
<Degi>
Lol the devkit has a PCIe connector but is as big as a mainboad
<azonenberg>
in case you're wondering why i have so much fiber in my house, btw, the vcu118s live literally on the far side of the house from my desk
<Degi>
Huh it has a 180 W power supply and no heatsinks
<azonenberg>
oh it has heatsinks
<azonenberg>
large ones, and fans
<azonenberg>
they just took them off for the photo op on the website
<Degi>
Hm I guess the pics just dont show them
<azonenberg>
that's pretty typical
<Degi>
Hmm what are you using them for?
<azonenberg>
it looks like an x86 cpu cooler
<azonenberg>
Right now? gathering dust :p
<azonenberg>
i was doing some asic design work a while back and the client bought them for me to use during prototyping
<Degi>
Lol that FPGA is almost as big as a PCIe x16 connector data lane part
<azonenberg>
they technically belong to the client, who hasn't asked for them back yet
<azonenberg>
and i doubt ever will
<Degi>
Huh it has a small zynq on top too
<azonenberg>
Yes. it has a zynq as a *management* processor, thats how big this thing is :p
<Degi>
Is the backside full of inductors and capacitors?
<azonenberg>
dont actually remember. Probably?
<azonenberg>
I have them bolted to 1U shelves
<azonenberg>
not easy to move
<azonenberg>
just hooked up to uart, jtag, power, and 40GbE
<azonenberg>
the QSFP28s are actually plumbed for 100g on the fpga side but i only had 40G optics
<Degi>
Lol
<Degi>
Can you stick them into a PCIe slot without breaking the slot?
<azonenberg>
oh and i hooked up the 1g phy too
<azonenberg>
Never tried
<azonenberg>
i imagine you would want to be careful and brace it somehow
<azonenberg>
my AC701 is actually the size of a large gpu
<azonenberg>
the vcu118 would stick out of a typical pc case
<azonenberg>
you'd have to run open
<Degi>
Like if it has some big heatsink on, it already looks pretty bad, but that'd probably be worse than GPUs... I bet you cant mount it horizontally heh
<Degi>
Or get a big case
<Degi>
PCIe expander, mount sideways
<monochroma>
i would just use a PCIe extender cable
<azonenberg>
monochroma: oh you're awake. perfect
<Degi>
According to LTT you can have like 3 meters of PCIe risers or so till the signal goes bad
<azonenberg>
We were just having some discussions about architecture for BLONDEL
<monochroma>
azonenberg: sorta
<azonenberg>
monochroma: just getting up or going to sleep?
<monochroma>
:o
<azonenberg>
what time zone are you running living in now? :p
<monochroma>
no clue :D
<monochroma>
i don't even remember when i woke up
<Degi>
I woke up at like 2:30 AM lol
<azonenberg>
sooo it looks like i am actually pretty closely aligned to Tokyo time right now
<azonenberg>
i got up around 15:00 PDT which is 0700 in Toyko
<monochroma>
weeb
<azonenberg>
monochroma: anyway, so the basic idea is to put an xc7a100t on BLONDEL that has a sodimm of ddr3, rgmii to the outside world, rmii to a stm32f7, and possibly XAUI to a TLK10232 if i want to put 10GbE on it
<azonenberg>
and then lvds inputs/outputs for trigger, la, and adc inputs
<azonenberg>
substantially all of the low speed status/control lines like sensor polling and gain/offset config would all be done via the stm32
<azonenberg>
Which would also be responsible for running the front panel display
<Degi>
Huh interesting, a thing on amazon is 3 € pricier when I open the same URL with a window where I'm logged in.
<azonenberg>
We can do the majority of the software development on an integralstick
<azonenberg>
Except for the front panel display, because i didn't break out all of the LCD controller lines i think
<azonenberg>
oh, so the other thing i will have to work out at some point is how to handle the fact that i'm going to have multiple ethernet interfaces on the board (1G and 10G)
<azonenberg>
to start i will probably have a soft mux on the front panel to select which to use, and simply not support both
<azonenberg>
but eventually my fpga ip stack will need to be multi interface capable
<azonenberg>
Putting 10G even on BLONDEL will be very nice for me because i am literally OUT of 1G ethernet ports at my main lab bench
<azonenberg>
But i have plenty of fiber
<Degi>
Lol
<azonenberg>
well ok... i have conduit and plugs
<azonenberg>
and coils of fiber sitting on the bench
<azonenberg>
that are not currently in said conduit
<azonenberg>
But the infrastructure is there if i bother to set it up :p
<Degi>
Can we have PoE on the scope
<azonenberg>
now you're talking feature creep lol
<azonenberg>
it would be possible with a respin of the fpga board
<azonenberg>
Not currently planning to support it
<Degi>
Okay
<Degi>
Well I guess one could stick a PoE to 12V splitter on there if required
<azonenberg>
Exactly
<monochroma>
lol poe scope
<Degi>
Huh this scope will probably use not so much power
<azonenberg>
monochroma: its not beyond the realm of possibility
<monochroma>
no, but an amusing thought
<azonenberg>
I just dont want to feature creep so far nothing gets done :p
<Degi>
Like we now have double the sample rate of scopes from 20 years ago for probably 1/30th of the power and less than 1/10 of the price
<monochroma>
yeah
<Degi>
Ah yes, ebay has a "10/100/1000 Mb/s" PoE thingie listed and in the description it says that its for 10/100 only
_whitelogger has joined #scopehal
<_whitenotifier-3>
[starshipraider] azonenberg pushed 7 commits to master [+15/-8/±3] https://git.io/JvNS2
<_whitenotifier-3>
[starshipraider] azonenberg 25f5bca - Updated antikernel-ipcores, moved old firmware to CLARKE directory
<_whitenotifier-3>
[starshipraider] azonenberg f5cc45e - Removed old SPLASH build scripts
<_whitenotifier-3>
[starshipraider] ... and 4 more commits.
hlzr has joined #scopehal
<azonenberg>
electronic_eel: i found a microwave guy in ##electronics! Say hi to hlzr :)
<Degi>
Huh theres an electronics channel
<azonenberg>
Degi: the SNR there is awful
<azonenberg>
but yes
<azonenberg>
i use it more as a place to meet people than for serious discussion
<Degi>
Hmm SNR? Is it being talked about electroncis at least?
<azonenberg>
sometimes :p
<azonenberg>
it just tends to be full of people who have no idea what they're doing
<azonenberg>
there's a few competent people but it gets noisy
<azonenberg>
a lot of people i know have left because of that
<Degi>
Ah yes, "you die when you touch a 100 A cable" like things?
<azonenberg>
That sort of thing, yes :p
<Degi>
I mean a 100 A inductor with loose connections on the other hand... lol
<azonenberg>
lol
<azonenberg>
mri magnet quench anybody?
<azonenberg>
i'm sure those are >> 100A though
<Degi>
Hm back when I was a kid I had some fun playing with a PC PSU PFC inductor and a 12 V battery haha
<Degi>
Or that giant ring core transformer I got from a supermarket scale. (WTF does that thing need that transformer for? Does the thermal printer work on steel too?)
<monochroma>
:O
<Degi>
Like that thing can do over 500 W xD I put some 6 mm² wire on it and use it for spot welding now heh
<azonenberg>
lol
<azonenberg>
oook so i'm finally sitting down to figure out where i left off on my systemverilog tcp stack. Spinning up a new bitstream for testing on integralstick
<azonenberg>
Problem #1 solved. It helps if you actually connect the clock to your logic
<Degi>
Ah yes there's a reason why ##electronics is a ##
<Degi>
Loll
<azonenberg>
You starting to see what i meant about low SNR?
<Degi>
Somebody is already talking about their dick
<Degi>
Like damn that is baaad
<Degi>
I guess the channel is kinda unmoderated?
<azonenberg>
i generally idle there but don't talk or even read messages unless somebody specifically summons me
<azonenberg>
Ops exist. They're... not very active
<Degi>
I think I'll probably leave that channel soon again lol
<azonenberg>
point made? :p
<Degi>
Yes lol
<Famine>
Degi, there are 2 semi regular ops and one of those ops is worse for disruptive crap than most people in there lol
<Degi>
lol
<azonenberg>
oh, so this is funny
<azonenberg>
Pico sells Tetris probes for much less than lecroy does (just without the probus interface)
<azonenberg>
but, and this is the funny part
<azonenberg>
they still call them Tetris
<azonenberg>
they don't rebrand them
<Degi>
Hm is tetris the brand name?=
<azonenberg>
Pico also openly acknowledges PMK as the manufacturer in the manual
<azonenberg>
Tetris is PMK's line of 1 to 2.5 GHz active voltage probes
<azonenberg>
Sold under the Tetris brand unmodified by Pico
<azonenberg>
And sold as the ZS1000, ZS1500, and ZS2500 by LeCroy after OEM customization to add a probus eeprom and connector
<azonenberg>
i assume this is done by PMK at lecroy's request, rather than mangling a factory Tetris unit. Probably a custom board spin with a slightly larger enclosure
<miek>
damn, those caddock resistors are pricey
<azonenberg>
how much?
<azonenberg>
i've been unable to even source the exact one used in the pp066
<azonenberg>
that was one of the reasons i started doing this probe
<miek>
i'm having trouble finding the exact one too, but they're in the region of £15-£35 each from what i can see on mouser
<azonenberg>
Still not a $1500 probe when you bolt that onto a sma and some coax
<azonenberg>
Lol
<miek>
lol, yeah
<miek>
$1200 for a lovely wooden box to ship it in
<azonenberg>
Lol
electronic_eel_ has joined #scopehal
electronic_eel has quit [Ping timeout: 256 seconds]
electronic_eel_ has quit [Ping timeout: 250 seconds]
electronic_eel has joined #scopehal
<azonenberg>
monochroma: so reading PMK's website a bit, it looks like the Tetris probes date to 2006
<azonenberg>
and the 2.5 GHz version dates to 201
<azonenberg>
2010*
<azonenberg>
i'm sure they were state of the art 14 years ago but... :p
<azonenberg>
Also i just found the Pico TA061 on PMK's website. It's the PML751, 875-751-000
<azonenberg>
500 ohms || 1.8 pF. Which sounds like a lot of capacitance
<azonenberg>
There is also a 100:1 version, also with 1.5 GHz bandwidth, and 5K ohms || 2.2 pF
<azonenberg>
Both 1.5 GHz bandwidth
<azonenberg>
So that answers my question as to why the TA061 looked so much like a PMK passive probe
<azonenberg>
It is one
<azonenberg>
i wonder why lecroy doesn't sell their own rebranded version of it
<Degi>
Hm I think I wanna build a 1 kV or 10 kV probe with 1 MOhm || 1 pF or so
<Degi>
Similar to the one from ice9 but smaller
<Degi>
Basically a coaxial capacitor with some resistors attached to it
<Degi>
1 Meg might be too low. More like 100 M or 1 G
<Degi>
That would be useful for debugging pulsed power circuits and general HV stuff
<miek>
i printed one of those probe positioners https://i.imgur.com/NKnCA4P.jpg still need to make some proper weighted feet, but machine screws work for now :)
<azonenberg>
miek: Nice. How did you get the measurements?
<azonenberg>
yeah the real thing feels like it has heft all the way through
<azonenberg>
i think its a steel core with injection molding around it
<miek>
ah, interesting
<azonenberg>
It's got the same density/feel as...
<azonenberg>
do you know what a "blue gun" is?
<miek>
no
<azonenberg>
it's a 1:1 scale replica of a real weapon made out of some kind of dense polymer and used in police/military training exercises, typically colored bright blue or red or some other color to make it clear to everyone involved that it's not a real gun
<azonenberg>
but has the same feel to build muscle memory etc, and is often cast around a steel core to give it the same weight as the real thing
<azonenberg>
i think these use a similar construction technique
<azonenberg>
they feel like plastic but have the density of metal
<azonenberg>
miek: and did you just make the "body" part from that zip?
<miek>
azonenberg: yup
<azonenberg>
are the feet hollow or what
<miek>
both the body logs and the feet have hollow cylinders, the idea is to glue in some steel rod
<miek>
legs*
<azonenberg>
i can get it made at shapeways in SLS nylon for $12.61, so if we could find something suitable for feet
<azonenberg>
it might be viable to semi-mass-produce these cheaper than i could buy PMK positioners lol
<miek>
heh :D
<azonenberg>
certainly a viable option for prototypes
<azonenberg>
More importantly, though, not being locked into the PMK positioners gives me a lot more options wrt body shape
<azonenberg>
although i would really LIKE to fit them if possible, it's nice to have a fallback option
<azonenberg>
so what are the "feet" parts, are they meant to be caps over the steel rod or something?
<azonenberg>
i feel like you can probably find commodity rubber feet that do the job
<miek>
yeah exactly, just caps over the rod
<azonenberg>
and ok if i want the same glass filled dark gray material that i was going to be using for the probe body, it's $16.51
<azonenberg>
tequipment sells the pico ta102 for $22.20
<azonenberg>
so probably not cost effective for high volume *if* i want exactly 1:1 the PMK shape
<azonenberg>
what i want to see is, can i DIY one for about the same or even a little more that is arbitrarily shaped?
<miek>
indeed, and it looks like the pricing would be at least in the same ballpark
<azonenberg>
Yeah. assuming we could find rubber feet that were suitable, and a source of suitably sized steel rods. Ideally prefabbed to size (screws or similar)
<miek>
stainless dowel pins are cheap and would probably come in the right length prefabbed
<azonenberg>
That's what i was thinking. basically i want to minimize work i or a tech would have to do on an assembly line
<azonenberg>
slapping a dot of glue in there and shoving a rod in is easy
<miek>
hah, that reminds me - i have a bag of them that are probably suitable :)
<miek>
hm, bit too long
<miek>
if we can't find the feet, do shapeways print in anything rubbery?
<azonenberg>
yes they have a thermoplastic polyurethane. No idea on pricing but likely expensive
<azonenberg>
Minimum size is 15x15x0.7 mm for it
<azonenberg>
i wonder why
bvernoux has joined #scopehal
<bvernoux>
hi
<bvernoux>
yeah after 3 weeks locked to UPS my SMA connectors are here !!
<bvernoux>
and they seems amazing and very high quality
<Degi>
Yay
<bvernoux>
Directly from Cinch Connectivity (Bel group now)
<Degi>
I have a bunch that dont look very golden anymore but they were like < 0.5 € per piece
<bvernoux>
mine are > 410 USD for 100 + more than 167euros for tax
<bvernoux>
but they cost more than 16USD/unit at DigiKey ;)
<bvernoux>
Now I shall solder them on my test PCB from OSHPark
<Degi>
Hm which PCB fabs make PCBs with higher quality materials?
<azonenberg>
what do you mean "higher quality materials"
<azonenberg>
any serious fab can make your board on any material you want, although it might be more expensive / longer lead time if you look for something exotic
<bvernoux>
In theory the perfomance shall be not far from Southwest Microwave expensive connectors ;)
<Degi>
PTFE etc
<azonenberg>
like i said, almost any serious fab. Right now Rogers RO4350B is my go-to material for higher speed stuff, Isola FR408HR for midrange, Isola 370HR for low end
<azonenberg>
I use oshpark for quick prototypes and multech for more high end specs
<awygle>
4350B and 408HR are so similar as to be almost indistinguishable
<azonenberg>
3.48 vs 3.68 Er
<azonenberg>
loss values are a fair bit different too
<azonenberg>
RO4350B has a loss tangent of 0.003 pretty stable across a wide frequency range
<azonenberg>
FR408 is like three times that
<bvernoux>
yes it is interesting to compare both it is my Plan
<azonenberg>
Generally speaking, if it's a low speed high density design i do 370hr at multech
<azonenberg>
if it's high speed i do 4350b at multech
<azonenberg>
if less dense prototyping i'll do fr408hr on oshpark
<bvernoux>
I have FR408 from OSHPark TRL Board v0.1 which I have updated to v0.2 as there was some things to fix ;)
<azonenberg>
and since i've already calculated the impedances etc, if i move to larger volume at another fab i'll keep the oshpark stackup
<bvernoux>
I will convert it to 2Layers RO4350B to check ;)
<bvernoux>
idea is to have 1.6mm board
<azonenberg>
did you look at my probe test board?
<bvernoux>
4 Layers OSHPark are more 1.5mm than 1.6mm
<azonenberg>
the new one on 2 layer 4350B
<bvernoux>
azonenberg, ha no I have not see the latest
<bvernoux>
I plan to buy a camera+microscope for next step ;)
<azonenberg>
now getting back to serious work on my tcp stack
<Degi>
Oh is that the internet stack
<Degi>
Neat
<Degi>
Hmm I think these cheapo SMAs need to be stored under inert gas, the 1.5 € cables look kinda blackish silvery instead of golden lol
<azonenberg>
Yeah. i have IPv4, UDP, ARP, ICMP all working in embedded server mode although i dont think i have the logic to initiate connections as i never needed it
<bvernoux>
azonenberg, do you have tested it in real conditions ?
<azonenberg>
TCP is still being added
<azonenberg>
bvernoux: i've done a lot of ping floods etc but this scope will be the first serious deployment of it
<azonenberg>
bvernoux: did you see my discussions the other day about the resistors on the probes btw?
<bvernoux>
yes a part as you are selecting final design with some 75Ohms
<bvernoux>
to have perfect match ...
<bvernoux>
or maybe I have missed something ?
<azonenberg>
100-75-75-75-75-50 is the string i plan to test in a day or two when they come in
<bvernoux>
as You was waiting 75Ohms
<bvernoux>
ha great
<azonenberg>
all 75s has a decent bit of rolloff
<azonenberg>
100 peaks by enough to compensate for most of that
<bvernoux>
I will buy some
<azonenberg>
the sim i did suggested 0.07 dB off from perfectly flat
<bvernoux>
do you have references ?
<bvernoux>
I can check them with my Peak LCR45 and of course with my VNA ;)
<Degi>
Huh what frequency are you designing it to?
<azonenberg>
references for what?
<bvernoux>
of the res
<azonenberg>
i just used vishay's s-parameter models
<azonenberg>
They went out to 40 GHz but i only looked at the portions of the curve from DC to 10
<azonenberg>
Degi: as fast as i can go :p
<azonenberg>
10 GHz is as far as i've run any of my simulations
<bvernoux>
I need to buy a batch and those vishay's RF cap seems very good and not too expensive
<bvernoux>
RF res ;)
<azonenberg>
bvernoux: i will definitely send you a full beta unit of the probe when it's done
<bvernoux>
yes DC to 10Ghz is still very good as so far I cannot validate at higher freq than 6GHz ;)
<azonenberg>
what i can say so far is, it's significantly higher bandwidth than either the ta061 or the zs1500
<bvernoux>
ha very great
<azonenberg>
both 1.5 GHz
<bvernoux>
and I saw you have also designed a nice case
<azonenberg>
the zs1500 is a nice clean rising edge but slow, and the ta061 has HF peaking like my design
<azonenberg>
but i plan to flatten that out
<bvernoux>
I hope the case will do not change too much caracteristics of probes as it is not so easy ...
<azonenberg>
I've done my testing in the enclosure
<bvernoux>
do you see big change with & without enclosure ?
<bvernoux>
I suspect there is some sort of capacitive/inductive ... effects with enclosure
<azonenberg>
I've never tested without actually, because the final tip has to be installed after the enclosure is attached
<bvernoux>
yes it is better to match all with final case
<azonenberg>
this is something i will be fine tuning in the respin, making some slight changes to the enclosure for mechanical reasons etc
<azonenberg>
The enclosure is glass filled SLS nylon and only pinches the board by the edges
<azonenberg>
there's an air gap over the coplanar waveguide
<bvernoux>
glass mixed with plastic/abs or something like that ?
<bvernoux>
SLS nylon interesting
<azonenberg>
shapeways mjf pa12
<azonenberg>
40% glass bead filled nylon 12
<azonenberg>
SLS
<azonenberg>
anyway that's for two reasons, one is to avoid any fields going through the shell and causing weird effects
<azonenberg>
the other is that i slide the populated board through a slot in the shell after manufacture
<azonenberg>
and so i need the silhouette of the resistors to have mechanical clearance
<bvernoux>
very interesting
<azonenberg>
I am respinning the probe board for mechanical reasons to have a slightly deeper tip so the new socket fits
<azonenberg>
as well as a wider part on the side for the ground lead
<bvernoux>
yes very nice
<bvernoux>
KeySight/Picotech will ask if they can buy and rebrand your probe ;)
<bvernoux>
at the same time they will increase the price by x5 ;)
<azonenberg>
lol
<azonenberg>
i have not seen *anybody* who ships serialized s-parameters with each probe
<azonenberg>
so that will be a nice way to stand out
<Degi>
Wonder if its possible to sell this scope to universities so stuff in didactic works doesnt have to be shown on some analog CRT scope lol
<Degi>
"I will not comment the packaging process. Here, everything is clear." *Game boss music starts playing*
<electronic_eel>
puh, finally finished reading the chat backlog - you've been productive today
<electronic_eel>
azonenberg: I like the project naming idea, now I'll just have to remember those names ;)
<electronic_eel>
about the different boards - you wrote the ext trigger is just sent straight to the fpga
<electronic_eel>
I don't know if we don't want the same comparator+protection logic as on the la for the ext trigger
<Degi>
Maybe with a bipolar DAC thi
<electronic_eel>
that would allow to use the ext trigger for several real world signals. otherwise the ext trigger is limited to circuits that are explicitly designed to work with this kind of scope
<electronic_eel>
about offloading some processing to a bigger stm32 - yeah, I think that makes sens
<electronic_eel>
e
<electronic_eel>
especially moving stuff like dhcp, tcp and so on into the stm32
<electronic_eel>
also monitoring
<electronic_eel>
about the different fpgas - I'm not familiar enough with them to help with that decision
<electronic_eel>
just that I think the more so-dimm slots the better: max mem available in so-dimm ddr3l is 16 GB
<electronic_eel>
if you have two slots, the scope could have 32gb ram
<electronic_eel>
a DUDDEL with 32gb ram and all 8ch sampling could sample full 4 seconds into ram, or 32 seconds with just one channel
<electronic_eel>
that completely obliterates all conventional scopes with their wfms/s figures
<electronic_eel>
chuck norris doesn't trigger, he just keeps on sampling
<Degi>
Thats kinda my goal with the PCIe adapter too
<electronic_eel>
Degi: put that into a common server with 2 TB of ram and you are ready to go ;)
<Degi>
Yes thats the goal
<Degi>
Uhm also like
<Degi>
1 HMCAD is 1 GB/s
<Degi>
You could have that in HDDs
<Degi>
86.4 TB a whole day
<electronic_eel>
hmm, if you have a bunch of hdds in raid 1 and write in parallel, that could work
<electronic_eel>
but I think scopehal needs a "slight" overhaul to be able to make any sense of that amount of data
<Degi>
Lol yes you cant cache that in ram
<Degi>
Maybe that could be useful for moon reflectometry
<Degi>
Shoot a high power pulse to the moon, measure reflection with 1 m diameter parabolic reflector and PMT tube and filter
<electronic_eel>
and what is the purpose of that?
<Degi>
Measure distance to moon
<Degi>
Idk just one potential application
<Degi>
Ohh wideband SDR
<electronic_eel>
ok, but why all the deep mem for that? don't you just need a precise counter for that?
<electronic_eel>
I mean the moon reflector
<Degi>
Hmm sure you could doo that
<Degi>
But why when you have several hundred gigs of ram xD
<electronic_eel>
I think the deep mem means you don't need any complex protocol triggers and so on in hardware/gateware anymore, you can just do it in software
<electronic_eel>
also let the software create a full list of events afterwards and make it easy to browse
<electronic_eel>
also no lost triggers due to limited wfms/s anymore, within the sampled time of course
deltab has joined #scopehal
<Degi>
Yes thats the idea kinda
<electronic_eel>
azonenberg: I thought some more about the LA input circuit. I think it would be nice to get a similar usable input voltage range as the other scopes have
<electronic_eel>
(setpoint about 20v, damage level about 40v)
<electronic_eel>
for example if you are working on an industrial controller, you could hook up the la straight to the 24v outputs
<electronic_eel>
they have some models for their probes in there. they seem to use a very similar technique like lecroy and rigol with about 100k impedance
<electronic_eel>
the voltage specs for these probes are also similar
<electronic_eel>
I have been thinking about how they do this. my current theory is that they use an opamp to attenuate the signal without a voltage divider (too high impedance, would kill freq) or too low impedance (would load the dut)
<electronic_eel>
maybe some kind of inverting configuration, but I haven't figured out how exactly
<electronic_eel>
but the inverting configuration would explain why for example Rigol offer to set negative thresholds - they would get them nearly for free with an inverting opamp
<Degi>
Why not capacitive dividers tho
<electronic_eel>
Degi: the la must work down to dc, I don't think you can do this with capacitive dividers
<Degi>
I mean capacitive resistive combined
<electronic_eel>
you mean a high impedance voltage divider for the low freq stuff and a cap divider for higher freqs?
<Degi>
Yes
<Degi>
Hmm I hope that 1.5 mm is enough clearance for 230 V lol
<electronic_eel>
from SELV to 230V? or between phase and neutral?
<Degi>
Ah you mean distance between small voltage and line
<Degi>
Hmm yes its a capacitive PSU, the whole thing is live
<electronic_eel>
1.5mm is borderline between phase and neutral, but I don't remember the actual values in the standard
<Degi>
I mean theoretically 0.5 mm should be fine lol. But I can put some hot glue over it
<electronic_eel>
hot glue won't help you, much too uncontrolled, can get moisture inside and so on
<Degi>
Better than air which gets metal dust inside
<Degi>
Hm the thing is I have 2.54 mm solder breadboard and there's two unused solder spots between L and N, I think the insulation gap is like 1.5 mm there
<electronic_eel>
better keep your live circuits protected from metal dust
<electronic_eel>
solder breadboard? you mean the protoboards with the holes and small copper rings around them, but just one sided?
<Degi>
Hm the green protoboards with through hole plating
<Degi>
Hmm I have one sided ones too but this one is two sided
bvernoux has quit [Quit: Leaving]
<electronic_eel>
with the one sided one you could remove the copper rings of two rows between phase and neutral. that should do it
<Degi>
Hm I usually do that but this is two sided and removing them is pretty ugh
<Degi>
Meh hot glue seems fine... Better than air probably
<electronic_eel>
but with the the plating you'd have to drill out the whole thing
<Degi>
No actually you can put your soldering iron at 450 C to it for a while and rip it out
<Degi>
But takes muuch longer than the one sided ones. (Also dont use cheap candle wax as an insulator, its about twice as good as air)
<electronic_eel>
whatever works for you, but don't leave the plating in or the clearance will be too low
<Degi>
Hm yes, hot glue it is
<electronic_eel>
then don't keep it connected when you are not around
<Degi>
Well of course
<Degi>
A software error could lead to it catching on fire lol
<electronic_eel>
now I try to build my mains circuits with the idea in mind that they are safe even when not supervised
<Degi>
Oh well this thing will probably explode sooner or later
<electronic_eel>
I know that that makes them more complicated and it needs some time to engineer all that
<electronic_eel>
but I think that is part of the fun of building such stuff
<electronic_eel>
and I take pride in making it safe
<Degi>
Maybe I'll make an actual PCB for this when it works properly. Would be useful for other things too
<electronic_eel>
what probably-will-explode circuit are you building?
<Degi>
SCR controller
<Degi>
With capacitive power supply
<Degi>
Till now only 4 components are recycled
<Degi>
Hm the only thing I've ever built that unintentionally catched on fire was the driving transistor of a SSTC. Like that was very foreseeable, considering that it dissipated 500 W into a very big CPU heatsink...
<Degi>
Usually I dont build things working at line voltage though...
<electronic_eel>
for full wave switching or phase control?
<Degi>
Its a triac for phase control, able to utilize both parts of the cycle though I probably only need one
<electronic_eel>
you need some big choke then to get the emi and mains distortion in check
<Degi>
Hmm idk
<electronic_eel>
what kind of power?
<Degi>
I could maybe do full phase switching too though that may overload the heating element
<Degi>
Single phase 230 V
<Degi>
Ahh
<Degi>
1 kW or so I think
<Degi>
Like the max is approx 3.3 kW
<electronic_eel>
oh! no phase control then!
<Degi>
But it shouldnt go that far, 1 kW max though testing is required
<Degi>
Hmm why tho
<electronic_eel>
that is evil
* Degi
laughs at the harmonics
<Degi>
So something like cycle stealing control would be better?
<electronic_eel>
because you will distort the mains for your whole street
* Degi
has PC with PFC of 0.8 and when everything is off the PFC is like 0.05 but that probably isnt too much harmonic distortion, mostly power factor...
<electronic_eel>
usually with these kinds of loads you do full wave switching
<Degi>
So 1 cycle on, n cycles off?
<Degi>
Hm when the current drain on mains is a square wave (different project) in phase with the voltage, would that be bad harmonic distortion or is that somehow acceptable? Somebody told me that's fine but I very much doubt so
<electronic_eel>
if it is a resistive heating element, you won't see any negative effects on the element or speed of control
<Degi>
Hm not sure if the element can blow up in 1/50 s or not at 3.3 kW
<electronic_eel>
yes 1 cycle on, n cycles off
<electronic_eel>
or n cycles on and 1 cycle off
<electronic_eel>
resistive elements aren't that fast to overheat
<electronic_eel>
this isn't some semiconductor
<Degi>
I think I will start with phase control and go to 200-400 W to bake the element and apply thermal conductivity coating. At 180 W I think there might be 50-100 °C delta T between the metal plate and the heating element. At 3.3 kW that would be 1000 °C... But the coating should fix that
<Degi>
But for 1/50 cycle that could be okay because of thermal capacity even without coating
<electronic_eel>
what do you want to heat with that thing?
<Degi>
An aluminium plate, mostly. Some pcbs but that thermal mass should be relatively small
<electronic_eel>
so a solder plate?
<Degi>
Yes
<Degi>
And for general heating of things
<electronic_eel>
I think 3.3kw is a bit over the top for that
<Degi>
(Curing epoxy, drying chemicals etc)
<Degi>
Maybe we can move to rpivate chat
<electronic_eel>
you don't want to torch your pcbs
<awygle>
2020 and kicad still doesn't have pin swaps
<Degi>
Pin swaps?
<awygle>
Can you import changes to the net list made in the pcb file back to the schematic? I doubt that works either...