<azonenberg>
electronic_eel: yes we are going back to 8087. I haven't updated the doc yet
<azonenberg>
Degi: In theory it would be possible to use interleaved 1511s or 1520s for BRAUN.
<azonenberg>
The 1511 frontend has 650 MHz full power bandwidth
<azonenberg>
so even the ZENNECK performance target is achievable with it
<azonenberg>
And you'd get a 12-bit mode using the 1520 which is nice
<azonenberg>
and you wouldn't need an FPGA with a boatload of transceivers
<azonenberg>
The challenge is, synchronizing all of those interleaved ADCs would get difficult. Five in particular is a very difficult number to use
<azonenberg>
four would allow much more easy phasing using different PLL channels
<azonenberg>
in either case, you would probably need an FPGA on the analog card. four 1520s means 44 LVDS lanes or 88 pins, which is too much for even a QTH-060, just for the data output
<azonenberg>
the 97600 has higher bandwidth - 1.2 GHz
<azonenberg>
So it still has a place on the upper end of the roadmap, but we might be able to squeeze one more design out of the 1520 if we interleave several
<monochroma>
they do make off the shelf SERDES ASICs primarily for LVDS->Serial applications
<azonenberg>
monochroma: that undoes the benefit of using the 1520 in this case though
<azonenberg>
namely, you no longer need an fpga with a huge number of fast gtps
<azonenberg>
what i find more attractive about interleaved 1520s is the option of doing 12-bit resolution at lower sample rates
<azonenberg>
keeping the 12 bit capability across most or all of the product line would be quite niec
<azonenberg>
nice*
<azonenberg>
The 7.6 bit resolution of the 97600 was a bit of a sour point for me
<azonenberg>
It may not save us anything in fpga capacity, given that many 1520s will need a ton of lvds io which might mean a just-as-big package
<azonenberg>
monochroma: btw, in the new BLONDEL architecture with stm32 as the management processor
<azonenberg>
what are your thoughts on running SCPI as the management interface?
<azonenberg>
i have nothing against the format for the purposes of management, performance there is noncritical
<azonenberg>
Just don't try and fit waveform data onto it
<monochroma>
mmm what software out there could talk to it?
<monochroma>
(other than scopehal)
<azonenberg>
i mean it would still use scopehal on the other end, but if someone wanted to write some other tools etc
<azonenberg>
easier to telnet in and send commands to tweak settings during debug
<azonenberg>
I am also contemplating not running ethernet to the stm32, or at least not supporting it in initial firmware
<azonenberg>
because switching frames by port number sounds painful and then i'd be running two tcp stacks etc
<azonenberg>
what if i instead had all tcp/ip on the fpga and bridged a uart or spi bus out to the stm32 for scpi traffic?
<azonenberg>
i.e. have the fpga consist of a unidirectional adc -> tcp pipe and a bidirectional uart <-> tcp pipe
<monochroma>
heh, yeah you could do that
<azonenberg>
we could then provide a pure uart / usb uart port on the back of the box for bringup, and not need to write a separate command shell
<azonenberg>
you would literally send scpi commands over a uart to configure the IP etc
<azonenberg>
(not necessarily proposing removing the LCD, but not making it a manadatory part of the architecture anymore)
<azonenberg>
have the fpga just be a uart mux: traffic coming in off either tcp or the ftdi would be sent into a fifo to the stm32, output traffic is echoed to both
<azonenberg>
run the internal uart at fairly high speed, say 3 Mbaud, which should be more than enough for control plane traffic
<azonenberg>
then the external at a more standard 115200 as it's only for initial config and debug
<monochroma>
so no support for multi connection usage i guess then?
<azonenberg>
I have no immediate plans to support that. Most "real" scopes do not support concurrent users
<azonenberg>
it will simplify the firmware a lot
<azonenberg>
my LeCroy's for example will only have one vicp connection open at a time
<azonenberg>
if you try to open a second the connection hangs. not sure if it even sends a syn+ack if there is an active client
<azonenberg>
but it certainly doesn't respond to any traffic
<monochroma>
lol
_whitelogger has joined #scopehal
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<azonenberg>
hardware status update: stencils for AFE characterization board came in
<azonenberg>
boards are still a week or so out probably
<Degi>
If we use 1520s its gonna be double the price of the 97600. We could use 4 HMCADs, I dont think thats too bad? Also yeah we'd probably need a QTH-090 or something... or put a FPGA on the sampling card to store it in RAM
<Degi>
The problem with splitting is that you need RF splitters now and signal will be attenuated. I'd rather avoid having 5 ADCs, since you'd have 1/8 the signal on at least 3 ADCs instead of 1/4 for 4 ADCs.
<Degi>
That still provides 3x nyquist at 650 MHz
<azonenberg>
So one hypothetical strategy
<azonenberg>
BLONDEL continues, what we've been working on now
<azonenberg>
DUDDELL continues as-is as well with one 1520 per channel
<azonenberg>
then eliminate BRAUN
<azonenberg>
and replace the planned 1x LM97600 on ZENNECK with four interleaved 1520s
<azonenberg>
With 1511s as an alternate build option for reduced cost
<azonenberg>
with 1520s you'd get your choice of either 4 Gsps 8-bit or 2.5 Gsps 12-bit, which is 8x and 5x oversampling respectively for a 500 MHz bandwidth target
<Degi>
Hm on BRAUN couldnt we do the same as on Zenneck but with 4 channels? And lower BW
<azonenberg>
what do you mean "with four channels"
<azonenberg>
My proposal is to take the LM97600 off the roadmap entirely
<Degi>
I mean braun is LM97600 with 4 channels, we could use 4x HMCAD with 4 channels
<Degi>
Oh wait
<Degi>
Thats already what DUDDELL does right
<azonenberg>
Yes
<Degi>
Lol yeah
<azonenberg>
BLONDEL = 4 AFE : 1 HMCAD
<azonenberg>
DUDDEL = 1 AFE : 1 HMCAD
<azonenberg>
Proposed ZENNECK = 1 AFE : 4 HMCAD
<azonenberg>
this would allow us to keep 12 bit resolution through the entire product line
<Degi>
Neato
<azonenberg>
With the option of 8-bit-only builds for the three lowest models as a cost-reduced alternative that would require only trivial firmware changes
<Degi>
Hmmm, yes a 1511 option wfor ZENNECK would be neat since that literally halves the ADC cost
<azonenberg>
i.e. forcing the already-present bit depth switch to 8-bit-only
<Degi>
Yes
<azonenberg>
Yeah, i'm designing for the 1520 as it's the higher spec unit
<azonenberg>
Let me update the roadmap, i like this idea. Never thrilled with 7.6 bit resolution
<Degi>
I mean later on we can always put a 1511 since its literally the same minus the 12/14 bit modes
<azonenberg>
Exactly
<azonenberg>
Also i plan to run all of the 12-bit HMCAD's at 625 Msps per ADC
<Degi>
Hm 625?
<azonenberg>
640 is the hard limit, but 625 is much easier to generate as an integer multiple of common clock sources
<Degi>
Oh okay
<Degi>
I mean 640 is 64*10 but idk
<azonenberg>
Yes but it has to be a divisor of a VCO frequency too
<azonenberg>
A VCO that also divides to 1 GHz
<Degi>
1520 has worst case 10.8 bits, also the 1520 has 700 MHz vs 650 of 1511. And maybe we should put a diff amp directly before the ADC with nothing inbetween (though that should be further evaluated before it turns out that the amp goes oscillatey) because of the input capacitance of the ADC
<Degi>
Hm right
<azonenberg>
Multiples of 640 in a reasonable PLL VCO range are 1.92, 2.56, 3.2 GHz
<Degi>
Hm the VCO we're targeting was 1.9-2.2 GHz or so right?
<azonenberg>
None divide to 1 GHz, and i want the 8-bit timebase to be 1 GHz to max out the ADC, as well as because it's a nice round timebase for measuring
<azonenberg>
The LMK0480x has four parts that differ only in VCO range
<Degi>
Cant we change the VCO frequency though? Like have 1.92 GHz for 12 bit and 2 GHz for 8 bit?
<azonenberg>
Yes, but you still have to find valid configs. And choose external loop filters that are compatible with both ranges
<azonenberg>
For best jitter performance i really want to keep the VCO constant
<Degi>
Hm okay
<azonenberg>
also because, at least on BLONDEL
<Degi>
What is 625 divisible to? 5 GHz?
<azonenberg>
i am using one pll for both acq cards. Which may be on separate modes
<Degi>
Hmm yeh
<azonenberg>
625 might actually not be what i was thinking
<azonenberg>
maybe it was 600
<azonenberg>
let me do some math, h/o
<Degi>
We could run it at 666 MHz from 2000/3 and that is only a tiny bit out of spec...
<Degi>
3000/5 is 600 MHz
<azonenberg>
yeah
<azonenberg>
that divides cleanly, is in range for the LMK04808
<azonenberg>
and a 3 GHz VCO allows us to easily create common sampling frequencies by dividing by multiples of 3
<azonenberg>
let me check the lmk0480x datasheet and see if odd dividers affect jitter or anything
<Degi>
Is it possible to "uncleanly" divide like 2.5 GHz to 1 GHz?
<azonenberg>
That may be possible too. I've used this chip before but am looking at the registers
<Degi>
Common sampling frequencies? Wont the ADCs always sample at either 600 or 1000 MHz (And maybe at 100 MHz for 14-bit mode) and then be decimated
<azonenberg>
Yes but we want to be able to do integer decimations if possible
<azonenberg>
i don't want a divided sample rate to be something stupid like 156.25 Msps
<azonenberg>
at least not if we can avoid it
<azonenberg>
ok so, PLL1 has a maximum phase detector frequency of 40 MHz. If the input is faster, you need to divide it
<azonenberg>
I suggest 10 MHz as a common value that also happens to be readily available from GPSDOs and OCXOs
<azonenberg>
And since we have to divide faster inputs to reach the phase detector anyway, might as well set input divide = 1
<azonenberg>
i.e. use 10 MHz input and not something faster like 100
<Degi>
I guess that works fine with this PLL? The ECP5 in the default PLL configuration has problems when the refclk is way lower than the VCO frequency, though I havent tried fiddling with loop bandwidth etc
<azonenberg>
well the ecp5 probably has a faster phase detector
<azonenberg>
this chip is meant for ultra low jitter
<azonenberg>
PLL2 has 155 MHz max
<azonenberg>
I guess 100 MHz with a div10 phase detector could work too
<Degi>
Yes it is possible to configure the phase detector on the ECP5 to be slower I think, havent tried it tho, now that I think about it.
<azonenberg>
I'm just spitballing here, not doing a serious design yet
<Degi>
Same
<azonenberg>
So, each of the PLL outputs has an analog delay in 25ps steps and a digital delay in VCO-tick units
<Degi>
Hm PLL2 has 155 MHz VCO and is fully integrated, right?
<azonenberg>
No. 155 MHz phase detector max
<Degi>
VCO tick is 1 cycle or something fasteR?
<Degi>
Ah
<azonenberg>
the VCO goes out to ~3 GHz and has a fairly narrow bandwidth
<azonenberg>
we need to decide which LMK0480x part we are using and choose a VCO frequency within its range
<Degi>
Yes I think that's what makes it low jitter... I measured the ECP5 VCO to go from 30 to 900 MHz...
<Degi>
(And that one has I think too much jitter for PCIe lol, it says to use external low jitter reference in thedatasheets)
<azonenberg>
anyway, for phasing multiple ADCs we need to mix both analog and digital delays and fine tune to get the most precise interleaving we can get
<azonenberg>
for BLONDEL, we just want to balance sampling time of the two acquisition boards to compensate for trace delay
<Degi>
Hm can we send a known low THD sine wave into it and then figure out the delays from that?
<azonenberg>
My plan for calibration, for the time being, is just to use my HDO9204
<azonenberg>
2 GHz BW, 40 Gsps
<azonenberg>
stick a probe on each acq board and tweak register settings until the traces line up
<Degi>
Hm for BLONDEL will the traces be routed length matched for the both ADC boards? That they're the same distance from the PLL
<azonenberg>
in fact, in equivalent time mode i can get 200 Gsps
<Degi>
Heh neat
<azonenberg>
Yes, they will be length matched. But always potential for process variation
<Degi>
My TDS520 can be set to 100 Gsps but it doesnt work at all over 1 Gsps doesnt even show samples lol
<azonenberg>
this may not end up being a per unit cal step, but i at least will want to verify phase alignment on the first prototype
<azonenberg>
anyway then each pll output can be programmed to any integer divider from 1 to 1045
<azonenberg>
PLL2 divider can divide by any integer from 2-8
<Degi>
I have the schematic of that in front of m, but I cant find the PLL1 VCO?
<Degi>
Ah is that for external VCOs
<azonenberg>
Yes PLL1 uses an external VCO. Typically a VCXO with a quite narrow tuning range
<Degi>
Hmm thats kind of a problem if we want 3 and 5 division
<azonenberg>
why? that's the vco divider
<azonenberg>
not the individual outputs
<azonenberg>
each output can divide by 1-1045
<Degi>
If the VCO runs at 3000 MHz and the VCO divider is at least 2, then in the node labelled "Clock Distribution Path" we could get max 1.5 GHz
<Degi>
And if one ADC board samples at 600 MS/s the other at 1000 MS/s thats kinda hard to od
<azonenberg>
Hmmm
<azonenberg>
So, here's an option i'm not thrilled about but will work for BLONDEL
<azonenberg>
Run at 500 Msps in 12-bit mode
<Degi>
Yes I thought about that too
<Degi>
Or external PLL from CPout1 to OSCin
<azonenberg>
And simply disallow 12-bit mode in 4 channel config
<azonenberg>
as it doesn't have enoguh sample rate
<azonenberg>
(which it wouldn't at 640 Msps either)
<Degi>
Hmm
<azonenberg>
in that case we have a nice integer value, we can use say a 2 GHz VCO (LMK04803)
<azonenberg>
with vco divide by 2
<azonenberg>
clock distribution path at 1 GHz
<Degi>
Oh at 640 MS/s its quite a bit below nyquist already heh. Guess 500 isnt too bad
<azonenberg>
Then DUDDELL is 1 Gsps 250 MHz, but in 12-bit mode at 500 Msps you're exactly at nyquist
<azonenberg>
we might want to look into a switchable lower bandwidth filter there or something
<Degi>
We can either use a second VCO or two PLLs maybe?
<azonenberg>
500 to 640 isnt enough of a difference for me to be happy
<azonenberg>
640 Msps is still light for 250 MHz bandwidth
<Degi>
640 is 2.56x nyquist
<azonenberg>
yes but filter rolloff
<Degi>
oh
<Degi>
Brick wall filter and then correct in post for phase?
<azonenberg>
ZENNECK will have a much more comfortable margin, 10x in 8-bit / 5x in 12-bit
<Degi>
Cant we just stack like 10 of the flat phase filters lol
<azonenberg>
that sounds huge. also they have rolloff in the passband which would get worse
<Degi>
Hmh
<azonenberg>
Anyway, ZENNECK will not have to worry about sharing pll channels though
<Degi>
Hm because 1 PLL for each channel because 4 ADCs?
<azonenberg>
Yes
<azonenberg>
the LMK0480x only has six independent divide/phase shift blocks
<azonenberg>
despite 12 outputs, they're paired
<azonenberg>
So we'd need a PLL per channel there. At the board level we'd just need phase coherent distribution of clocks to each acq board
<azonenberg>
at the main board level*
<Degi>
Is the digital delay in steps of VCO/VCO divider cycles?
<azonenberg>
see the block diagram in 8.2. It's in steps of clock-distribution-path ticks
<azonenberg>
So 1 GHz distribution path with 2 GHz VCO would give us 1ns per digital step, then 25ps per analog step for fine phase tuning
<Degi>
Yes I was just wondering because the ECP5 somehow manages to be in 1/8th of a VCO cycle somehow
<azonenberg>
I'm not dead set on this PLL
<azonenberg>
it's just one with very good specs that i'm familiar with
<azonenberg>
i suspect fractional vco stuff has higher jitter
<azonenberg>
this one is specifically tuned for low jitter
<Degi>
Yeah maybe later I can search for other PLLs too, I'll leave soo and be back in a few hours...
<azonenberg>
FPGA PLLs are optimized for flexibility
<Degi>
Yes haha and have bad jitter
<azonenberg>
not as bad as DCMs at least
<Degi>
DCM?
<azonenberg>
Digital clock manager
<azonenberg>
it's what spartan-6 had instead of a true pll
<azonenberg>
basically, it's a pll where instead of an analog charge pump and VCO, you build it entirely out of standard cell logic
<azonenberg>
the output clock is generated by a RING OSCILLATOR with variable tap size
<azonenberg>
and you just mux inverters in and out of the delay line to vary the oscillator period
<Degi>
And it varies the tap size very fastly to keep the frequency constant?
<Degi>
Oh geez that is BAAD
<azonenberg>
They are extraordinarily sensitive to PTV variation, and the taps are like 50-100ps apart
<Degi>
I guess if it somehow works?
<azonenberg>
so when it steps, you get a huge shift
<Degi>
PTV?
<azonenberg>
a DCM is a jitter generator masquerading as a PLL
<Degi>
So it has at least 100 ps jitter?
<azonenberg>
process, temperature, voltage
<azonenberg>
Well, it depends on how closely your incoming signal aligns to a multiple of the tap size :p
<azonenberg>
if it never changes taps, great
<Degi>
Lol
<azonenberg>
but in reality it ends up dithering between two taps
<Degi>
If the input signal is just as noisy in the same pattern as a ring oscillator?
<azonenberg>
sec, i got some GREAT screenshots earlier
<Degi>
I once built a ring oscillator out of BFP420s and it had like a few tens of MHz BW at uhm 190 MHZ?
<azonenberg>
Top trace is a moving average of the clock period
<Degi>
Uhm what
<azonenberg>
bottom is a lowpass filtered version of the fpga's vccaux rail
<Degi>
Does anything work with that?
<azonenberg>
you're seeing a stacking of two effects
<azonenberg>
first, the output is jittering between two ring oscillator taps
<Degi>
Geez 75 mHV
<azonenberg>
second, the tap size is changing in sync with power supply noise
<azonenberg>
because, well, it's a ring oscillator
<Degi>
I mean that jitter is already bad without the switching
<azonenberg>
and then the feedback loop is trying to compensate for that
<azonenberg>
but then the supply voltage changes, which throws everything off
<azonenberg>
This board had grossly inadequate decoupling
<Degi>
Oh and the continuous frequency change is the voltage variation
<azonenberg>
It wasn't my design
<Degi>
Hahaha
<azonenberg>
Correct. The squarewave is the native DCM jitter
<azonenberg>
then it's modulated by the supply voltage
<Degi>
Which is influenced by the clock frequency?
<azonenberg>
i have no idea what the actual noise source was
<Degi>
Lol maybe I can try to implement that in FPGA logic sometime haha
<azonenberg>
didn't debug that far
<azonenberg>
this screenshot was enough to be a smoking gun
<azonenberg>
i plotted against VCCINT and there was no correlation
<azonenberg>
the correlation here is obvious enough a caveman can see it
<Degi>
Is VCCINT the fabric voltage?
<azonenberg>
Yes
<azonenberg>
On Spartan-6, VCCAUX runs the DCMs, LVDS input buffers, and a few other odds and ends that need higher supply voltage
<azonenberg>
analog-ish thingies
<Degi>
Maybe you should take a look at https://codeberg.org/x44203/Scope I designed a time interval (with start stop pulse where stop can be triggered multiple times, only the first is counted, suited for comparators)
<Degi>
Hehe
<azonenberg>
so what is the goal of this circuit? a time to digital converter?
<Degi>
It converts time to analog
<Degi>
Needs a sorta fast ADC after that (depending on transistorl eakage)
<azonenberg>
Sooo let me think more about requirements of the actual system
<azonenberg>
i don't think this will quite work
<Degi>
Hm I think IRL it'll perform way worse than in the simulation because I didnt model all the traces...
<azonenberg>
well no, i'm concerned about interface specs
<azonenberg>
What we need is something that can be armed, then records the time from comparator rising edge to clock rising edge
<azonenberg>
(both as LVDS or similar)
<azonenberg>
and then ignores subsequent edges on either signal until re-armed
<Degi>
Yes
<Degi>
Reset arms it, then it measures the time between start and stop
<Degi>
And ignores subsequent signals
<azonenberg>
but is it differential?
<Degi>
Hmm no... You could add a transformer tho
<azonenberg>
thats one of the challenges - getting single ended stuff this fast lol
<azonenberg>
you could use one leg of a diff signal i guess
<Degi>
Lol according to sim it works, though I used I think 100 MHz for clock
<Degi>
I mean for the comparator signal you can convert the PECL to a single ended signal with PCB air core transformer
<Degi>
It needs a few nH thats sufficient as long as the rise is fast enough according to sim
<lain>
did you model component tolerances and parasitics?
<lain>
might not matter at these speeds though
<Degi>
Hm only a few
<azonenberg>
lain: well we're not putting a TDC trigger in BLONDEL
<azonenberg>
this is more R&D for future scopes
<azonenberg>
so i want to target something a lot faster
<lain>
ahh
<azonenberg>
lain: also, we've changed our roadmap around a bit
<Degi>
I mean we could its like 30 bucks
<azonenberg>
I'm nixing the LM97600 based scopes
<azonenberg>
7.6 bits is not very good at all, and you need a lot of serdes to keep up with all of those 5 Gbps data lines
<azonenberg>
So i am thinking of having DUDDELL be 1x AFE : 1x HMCAD1520
<azonenberg>
remove BRAUN, the 350 MHz scope
<azonenberg>
then make ZENNECK, the 500, be based on four interleaved HMCAD1520s
<azonenberg>
this would give us 4 Gsps 500 Msps (8x oversampling) in 8 bit mode
<azonenberg>
but also let us do 12-bit resolution
<Degi>
Ill be back later cya
<Degi>
And the sim now has the transistor models in the same folder, it should be possible to sim it now when that file is moved to your ltspice directory (if you ahve that installed)
<azonenberg>
lain: also 640 Msps on the HMCAD1520 is difficult to generate. it doesn't divide, well... anything cleanly
<azonenberg>
we're debating lowering the 12-bit sample rate to 500 Msps
<lain>
ahh
<azonenberg>
625 would work, except 625 and 1000 don't have any common multiples within normal VCO ranges
<azonenberg>
you'd have to go up to 5-10 GHz PLL frequency
<Degi>
600 and 1000 works if we can find a PLL with 3 GHz which can do div by 3 and div by 5 at the same time
<Degi>
(Or add a second VCO to the one we already have)
<Degi>
ttyl
<azonenberg>
Degi: yeah. But is it worth that effort given that 600 MHz is also an awkward number that means your timebase isnt' a round number in ps?
<azonenberg>
lain: however, this would mean that the sample rates for BLONDEL would drop to 250 and 125 Msps in 2/4 channel mode
<azonenberg>
in 12 bit resolution
<azonenberg>
So you *will* get aliasing on 4 channel 12-bit mode if you have any frequency content beyond a few tens of MHz in your signal
<azonenberg>
debating just disallowing that mode in firmware
<azonenberg>
also WOW... mini-circuits just announced that they're partnering with mouser for distribution
<azonenberg>
Too bad it's not digikey, but still having their products more accessible instead of buying on the minicircuits website will be nice
<Degi>
Uhm even at 640 over 4 wed get aliasing right?
<azonenberg>
Yes. Which is why i'm not upset about going to 500
<Degi>
Hm isnt mini circuits already partially on mouser?
<Degi>
Yes same
<Degi>
I found some filters of them on mouser quite a while ago
<Degi>
What are the up/downsides digikey vs mouser? Is it mostly just delivery stuff?
<azonenberg>
Digikey's main warehouse is two states away from me and i find their search to be a lot nicer
<azonenberg>
And generally you either want speed or bandwidth, it's rare you would need high speed *and* precision. So for the lowr end scopes i am find with 12-bit mode lowering the sample rate or BW a fair bit
<Degi>
Hm right
<azonenberg>
what i want to avoid is silent aliasing
<Degi>
Well idk mouser has a warehouse in the EU but ships from texas? to me
<Degi>
Hm can glscopeclient show warnibngs?
<Degi>
Like you could use the 14 bit mode as a voltmeter heh
<azonenberg>
Currently? no. And lol
<azonenberg>
you know i'm curious what the adc lecroy used in the wavesurfer 3000 series is
<azonenberg>
i doubt it's an asic at that price point
<monochroma>
if they churn out a bunch of ASICs they probably have some corners that don't run super well ;)
<Degi>
Do you have one or know somebody who does?
<azonenberg>
Degi: I had one, past tense
<azonenberg>
Sold it to $dayjob when i got the HDO as i only had space for two scopes in my lab
<azonenberg>
and what was i gonna do with a 350 MHz scope with a 10" screen when i had two 15" screened GHz bw scopes?
<Degi>
Hm 1 GHz 4 GS/s whats the price?
<Degi>
Huh isnt 15 inch like 40 cm?
<Degi>
There are ADCs from I think AD or TI which do 1 GS/s with 2.5 GHz BW
<Degi>
They cost 50-200 bucks
<azonenberg>
Degi: i believe they are using 2 GS/s ADCs
<azonenberg>
because they have 2 GS/s on all channels or 4 GS/s on 2
<azonenberg>
It's annoying, there arent a lot of teardowns of scopes in this class
<azonenberg>
people don't want to buy multi-thousand-dollar scopes to take them apart
<Degi>
20 Mpts memory?!
<Degi>
I guess they cheap out on ram lol
<azonenberg>
but it's not "cool" enough compared to like a labmaster
<Degi>
Its 2020 lol
<azonenberg>
Degi: they use an am335x as the soc
<azonenberg>
this is also a 2015 or so model, its not current
<azonenberg>
the cpu is slooow and the ui lags
<Degi>
I mean still back in 2015 a gig of ram sure wasnt that pricy
<Degi>
Loll
<azonenberg>
it's a beaglebone plus an fpga running windows ce
<Degi>
I mean the TDS520 has like 50 kPoints or more and that thing is 20-30 years old...
<Degi>
Whyyy okay
<azonenberg>
it's nothing like lecroy's high end scopes... my hdo can do up to 64 or 128M points
<azonenberg>
it has literally a touchscreen laptop display on it, a... ivy bridge? i5
<azonenberg>
and i think 16GB of RAM
<Degi>
If I can get this PCIe thing working I could do like 90000 Mpoints on the recycled server
<azonenberg>
lain/monochroma: anyway, what are your thoughts on the 12 bit mode on BLONDEL?
<azonenberg>
i dont want to remove it, it's a major benefit over the cheap 8 bit scopes. but we are limited on sample rate
<azonenberg>
do i only allow it in 1/2 channel mode?
<azonenberg>
do we add a switchable AA filter (lots of work)? Do we just warn the user to use an external band-limiting filter if using 4ch 12b mode?
<lain>
640 MS/s is an integer number of fs
<azonenberg>
lain: :p
<Degi>
I think warning is best option
<Degi>
fs?
<lain>
femtoseconds
<azonenberg>
i mean we want some means in glscopeclient to display channel overload warnings etc anyway
<Degi>
Lol
<Degi>
I thought that meant sample frequency or something
<lain>
azonenberg: switchable AA filter is what I would do
<Degi>
Hm also for the scope display after configuration, maybe it can show current status? Like sample rate and which channels are active or overloaded
<azonenberg>
degi: yes thats a possibility
<azonenberg>
lain: that adds a lot of complexity
<azonenberg>
since you have to avoid unterminated stubs from the various paths
<Degi>
Lol diff relais cost 15 bucks each but you can get 2 channel diff "USB switches" for 2.5 €
<Degi>
The signal path would alwayys be terminated and unused filters dont need to be terminated
<azonenberg>
why? they're unterminated stubs
<azonenberg>
they also contain resistors or caps to ground that load the signal
<Degi>
Hm I mean the unterminated filter would have no signal on it right?
<lain>
azonenberg: sooo you can buy varicaps (variable capacitors) which can be used to construct an adjustable low-pass filter
<Degi>
The unconnected filter just stays unterminated, since there is no signal on it. The relais are on input and output of the filter, switching the path between 2 different filters
<Degi>
I think that would be a very bad idea
<Degi>
We wanna do DC after all
<lain>
that's actually how most scopes do it afaik
<azonenberg>
degi: so here's an idea
<lain>
is to use varicap-based filters
<azonenberg>
what if we had two SPDT RF relays
<azonenberg>
and set it up like a three way light switch
<Degi>
Yes thats what im saying
<azonenberg>
power flows from point a to point b through either the upper or lower path
<Degi>
But differential spdt
<azonenberg>
this would be single ended on the input, before the gain stage
<Degi>
You can do that with 1 USB IC since it has two SPDT switches inside lol
<azonenberg>
offset*
<azonenberg>
hmmm you want a solid state switch?
<Degi>
No
<Degi>
Only if we wwanna go real cheap lol
<azonenberg>
do you have any idea what frequency response of the analog muxes look like?
<azonenberg>
This is a good reference design to borrow ideas from
<azonenberg>
But i don't want to copy it
<Degi>
Hm yes but the basic structure is a starting point
<Degi>
See ya later
<azonenberg>
lain: so i guess we'll want to add additional relays and not exactly use the cirucit from the characterization board
<azonenberg>
but if we mux between two copies of the same attenuator with different passive values i'll be pretty happy
<azonenberg>
easiest option is probably to just have a 50 MHz version of the same filter
<lain>
I want to design a very broadband low- and high-pass filter pair (for use as a broadband tunable bandpass filter in SDR)
<lain>
but it's going to be $$$ I suspect
<azonenberg>
Yes for an entry level scope i want to KISS
<azonenberg>
So my thought is, have a 100 and 50 MHz filter we mux between
<azonenberg>
Mandate the 50 MHz bandwidth limiter in 12-bit mode
<azonenberg>
allow it to be switched in for 8-bit operation on the user's request
<azonenberg>
wooo my resistors are now at the local post office and delivery date is updated to today
<azonenberg>
by 12:30
<azonenberg>
lain: i think within the next day or so, i should have rx-only tcp working
<azonenberg>
you won't be able to send traffic but it will accept anything you feed it
<azonenberg>
and pass it on
<azonenberg>
My thought is to hook that up to a uart going to the stm32 on my integralstick
<azonenberg>
Then switch to software and start building a quick mockup of the SCPI interface
<azonenberg>
with incoming commands delivered over tcp from the fpga, and response data going out a stm32 uart to GPIOs
<azonenberg>
so commands in via telnet scpi, responses coming out over ftdi uart
<azonenberg>
do a bit of software tinkering on that, then finish the tx side of the tcp stack
<azonenberg>
and get the whole interface working over tcp
<lain>
sounds good
<azonenberg>
at that point, once commands actually reply over the same socket, i'll be able to start work on a very preliminary scopehal driver for the system
<azonenberg>
all of the actual firmware-side back ends will be nops or mocks, of course
<azonenberg>
since my integralstick lacks an AFE to talk to
<_whitenotifier-3>
[starshipraider] azonenberg pushed 1 commit to master [+0/-0/±1] https://git.io/Jvxa3
<_whitenotifier-3>
[starshipraider] azonenberg a29a82f - Updated README with changes to roadmap
<azonenberg>
lain: soooo hmm
<azonenberg>
You remember my concept cad sketch of the BLONDEL enclosure and guts right?
<azonenberg>
blue thing is the lcd, yellow cylinders are the probe inpu
<azonenberg>
input SMAs
<azonenberg>
ext trig and LA connectors not shown, rear panel connectors not shown
<azonenberg>
So my original concept called for two 4ch AFE+ADC boards right behind the SMAs, some kind of board on the right side with the external trigger and LA probe connectors
<azonenberg>
the main fpga board along the back of the case
<azonenberg>
(all attached via q-strips)
<azonenberg>
and then behind the lcd, a board with a stm32 attached via a 100 mil header that drove the display and didn't do much else
<azonenberg>
The new plan calls for the stm32 having much more of an active role in the control plane, and being responsible for driving dacs and such
<azonenberg>
So i'm wondering if i should have a mostly passive (2L even?) board that just adapts the lcd's attached FFC to a q-strip and mates with the fpga board
<azonenberg>
and move the stm32 to the main board, rather than having a bazillion spi/i2c buses crossing the connector
<azonenberg>
Another option would be an L-shaped main board, rather than two, but i feel like this would be a lot more annoying to assemble and waste a lot of panel space
<azonenberg>
"fits in my current reflow oven" is a hard bound on board size
<azonenberg>
Which means the main logic board should not be more than about 275 mm wide
<lain>
hmm
<azonenberg>
I'm thinking of it taking up about the center ~half of the chassis
<azonenberg>
left right wise, and the back half front-back wise
<azonenberg>
then LCD and LA boards that go back far enough to mate with it
<azonenberg>
lain: proposed mainboard, LCD board, LA board, and analog board floorplan
<lain>
hmm yeah
<azonenberg>
exact dimensions subject to change, but basically the analog boards will overlap the main board in the middle, with enough sticking out to either side for a qth-030 to the trigger/la and lcd boards
<lain>
of those options, I like the idea of adapting the lcd ffc to a qstrip and just putting the stm32 on the mainboard
<azonenberg>
Yes
<azonenberg>
there might be a backlight boost converter on that board
<azonenberg>
but it will be otherwise passive
<azonenberg>
the la/ext trig board will have a trigger comparator and front end
<azonenberg>
probably qth-030 to the two side boards, qth-060 to the analog boards
<azonenberg>
Another option re the LCD is to have a tiny board, not mating with the mainboard, that just bridges the lcd ffc to another ffc
<azonenberg>
and have a long flex ribbon cable going to somewhere on the mainboard
<azonenberg>
the ffc connector is likely cheaper than a qstrip, but might have worse SI
<azonenberg>
custom flex for that is also a possibility
<monochroma>
IDC ribbon cables are cheep
<azonenberg>
That's an option too
<azonenberg>
the advantage of using a cable vs a rigid board is we don't need to overlap the mainboard
<azonenberg>
we can come in behind the analog boards or something
<azonenberg>
and thus have more flexibility wrt size/placement of the main board
<azonenberg>
also lol my pico probes i ordered like 3 months ago finally shipped
<azonenberg>
Picoconnect 921, 20:1 AC coupled 6 GHz gigabit probe
<lain>
lol
<lain>
took a little while
<azonenberg>
also packages on my front steps woo. lets see if i have my resistors
<monochroma>
resistance is futile
<azonenberg>
Probe assembled w/ 75R's
<lain>
:D
<Degi>
Neat
<Degi>
Why have a Q strip on the display?
<Degi>
Yes ribbon cable sounds good
<monochroma>
because azonenberg is addicted to them. i have seen him crush them up on his bench and snort them :<
<Degi>
Like how does the display need to display 4k 60 Hz?
<Degi>
owo
<lain>
hey that's what I do with anime figures
<azonenberg>
Degi: no its just a dense high pin count connector. i'm open to other options
<azonenberg>
once i work out how many signals, how fast, are invovled
<azonenberg>
100 mil headers could work, or some kind of ribbon
<Degi>
Like the QTHs cost a bunch of money. I understand that for high speed signals but for a display ribbon would be OK
<monochroma>
is it going to be anything other than a SPI OLED ?
<Degi>
Well we could attach a 4k 60 Hz screen heh
<azonenberg>
monochroma: the one i have picked out now is a parallel rgb tft
<monochroma>
oled or bust
<Degi>
I'd prefer LCD over OLED
<monochroma>
why D:
<azonenberg>
480x116 full rgb with captouch
<Degi>
Because burn in and power usage
<Degi>
Oh neat, captouch!
<azonenberg>
my plan was for it to sleep when not in use
<azonenberg>
any touch will wake it up
<azonenberg>
since 99% of the time, you wont be using the display
<Degi>
WE can have soft inputs for IP address too
<monochroma>
cap touch D:
<Degi>
Maybe we can have the display show the scope status and "sleep" be darkened or off backlight
<azonenberg>
Degi: that is why i put the touch on there. initial ip config
<Degi>
Neat that way we have no buttons
<azonenberg>
exactly. a normally-off lcd that blends into the front panel when not in use will give it a nice clean look
<azonenberg>
soooo
<monochroma>
cap touch display on a 1U ? D:
<monochroma>
tiny
<azonenberg>
yes
<azonenberg>
480x116, 3.8 inch diagonal
<azonenberg>
just shy of full 1U height
<azonenberg>
it is expressly made for this purpose
<monochroma>
lol
<azonenberg>
635-1201-ND
<azonenberg>
can probably get an equivalent cheaper
<azonenberg>
but that's what i'm using in the first prototype
<monochroma>
oh i've worked with matrix orbital LCDs before
<azonenberg>
you can see the overshoot in the signal when fed right into the scope
<lain>
azonenberg: niiiice
<Degi>
Hm how do you measure the signal? You said you have a 50 ohm termination you measure off of, right?
<azonenberg>
it's slightly rounded off in my probe trace, which makes sense given that it's a longer cable and through an attenuating probe
<azonenberg>
Degi: you mean what am i probing? or what
<Degi>
Yes
<azonenberg>
One of LeoBodnar's 40ps risetime pulse generators
<Degi>
Maybe that termination has some inductance? Or the probe loading, which changes the resistance to 45 ohms
<azonenberg>
i put a bnc-sma adapter on the BNC
<azonenberg>
then a SMA 50 ohm terminator
<azonenberg>
then hooked my probe on the back side of the pcb across the bnc center contact to ground
<azonenberg>
aaaanyway, i think this probe is as good as it's going to get electrically
<azonenberg>
I'm going to work on the mechanical respin tonight
<Degi>
Hm do you have a picture? Is the adapter a PCB?
<Degi>
Hm yes the probe is neat
<Degi>
Wait why does the 40 ps risetime generator have a BNC?
<Degi>
I found its webpage
<azonenberg>
he makes bnc and sma versions
<azonenberg>
i bought the bnc because that's what my scopes have
<azonenberg>
it's meant to plug directly onto a scope for testing scope performance
<Degi>
Ah
<azonenberg>
anyway, i put a Pomona 4291 (Digikey 501-1338-ND) into the BNC
<azonenberg>
and capped it off with an Amphenol RF 132360 terminator (ACX1251-ND)
<azonenberg>
and probed at the solder side of the BNC using a Pico TA064 pogo pin as the tip (can't use the PMK ones on this board spin, they're too short)
<azonenberg>
with a PMK 890-400-800 ground lead
<azonenberg>
Is that sufficient detail for "how am i measuring" ?
<azonenberg>
:)
<Degi>
And you probed on the pulse generator backside?
<azonenberg>
Correct
<azonenberg>
Tip on the center bnc solder right where the coupling cap joins it
<monochroma>
no, we require schematics, a full detailed report, and NIST tracing
<Degi>
^
<azonenberg>
and ground to one of the four corner pins of the bnc shell
<azonenberg>
my probe vs lecroy/pmk 1.5 GHz active probe
<Degi>
Hmm can you do a fourier analysis on both
<azonenberg>
my edge is much faster and less rounded, and you can actually see that same overshoot on the zs1500 plot too. Just all blurred and smoothed out
<azonenberg>
Degi: In a bit, i have other stuff to do
<azonenberg>
My takeaway from today's experiment is that my probe is now very close to flat and has >> 1.5 GHz bandwidth, confirmed by tests against both the pmk active and passive 1.5 GHz probes
<Degi>
Lol "I don't see any good way to get to a sub picosecond (less than a trillionth of a second) rise time," https://www.eevblog.com/forum/testgear/40-ps-rise-time/ not sure if you can even do that with copper cables
<azonenberg>
hey lain - when i drop off the stuff tonight can i give you a probe/tip/ground and the pulse generator? i want to see a plot off your 5 GHz scope in RIS mode
<lain>
azonenberg: sounds good
<azonenberg>
you can return it when i do the grocery run next week
<Degi>
Heh do you live nearby eachother?
<lain>
yah :3
<Degi>
Neat
<azonenberg>
Degi: i used to live a mile from her and monochroma
<azonenberg>
moved the next town over when i bought the house
<Degi>
Hm that's certainly faster than shipping stuff halfway over the world heh
<azonenberg>
Lol
<azonenberg>
I'm going back to their area tonight because i'm helping to gear up medical reserve corps doctors for working at a coronavirus testing center
<Degi>
Oh nice
<azonenberg>
they all need to be fitted for masks and such and i'm one of the volunteers trained on the testing procedure
<Degi>
Hm you test masks whether they're good enough?
<azonenberg>
Not testing the mask
<azonenberg>
testing the fit of the mask to the wearer
<Degi>
Ah yes, that's important
<azonenberg>
different size/shape faces fit different masks better
<azonenberg>
basically stick a plastic bag over your head, spray in some bitrex or saccharin, confirm you can taste it
<azonenberg>
repeat with the mask on, confirm you cannot taste it
<Degi>
I have like a mask which I think actually makes the air quality worse when you use it lol
<azonenberg>
repeat moving your head around, turning, bending, talking, etc
<Degi>
Neat
<azonenberg>
if you detect the aerosolized test agent at any time you fail, adjust fit or try another mask and repeat
<azonenberg>
if you can't smell or taste it by the end you have a good fit
<azonenberg>
this is a standard OSHA procedure
<azonenberg>
last round only 2 of the 6 people we tested fit the FEMA-issued masks well
<azonenberg>
we traded the other folks' masks for ones our group had of a different model that was a better fit for their faces
<Degi>
Hm yeh I find masks pretty oof. Even the ones with bendable parts dont fit so good
<azonenberg>
that's me just after putting in a solvent based epoxy floor on the other half of my lab in the background
<azonenberg>
the VOC sensor on my phone pegged at over 5000 ppb, the actual level was far higher
<azonenberg>
through the mask i didnt smell a thing
<azonenberg>
I like full-faces because if you wear a respirator you almost always need eye pro too
<azonenberg>
and glasses plus a half face tend to fog up from sweat etc
<azonenberg>
the 6900 at least is an ingenious design, inhaled air is drawn through the filters then into the face cavity
<azonenberg>
then through a check valve into the mouth/noise cup
<azonenberg>
so you are sucking clean, cool, low-humidity outside air over the lens each breath
<Degi>
Hmm idk maybe I should wear respirators more often
<azonenberg>
it *never* fogs
<miek>
i've not gone full-face, but i really like the 3m 65xxQL
<monochroma>
is this how cybergoths come back into style?
<azonenberg>
also the whole perimeter of your face is a seal, so you dont have any uncomfortable pressure on the bridge of your nose like i've noticed with a lot of half face or disposable ones
<Degi>
Like that one time a few days ago I arc melted a zinc coated screw and then opened the balcony door pretty quickly cause the aerosols were oof
<monochroma>
mmmmm weeks long zinc cough
<Degi>
Not that much zinc lol
<Degi>
Hmm I can only find the 6800 to buy for some reason
<Degi>
Well for 37 € taht looks pretty good actually
<azonenberg>
The 6000 series consists of six models
<azonenberg>
6100, 6200, 6300 are half face small/medium/large
<azonenberg>
6700, 6800, 6900 are full face small/med/large
<Degi>
The visor is neat
<Degi>
Looks good for soldering
<azonenberg>
The masks arent super hard to find these days, but filters? good luck
<Degi>
I can just stick a hose to the balcony lol
<azonenberg>
i'm running off my inventory from doing construction on the house
<Degi>
Lol one of the amazon questions "which filters do you need for virus defense"
<Degi>
Hm how good is the fit? Like how can I be sure that it fits my head before buying it?
<azonenberg>
Degi: You can't. Lol
<azonenberg>
The only way to know is to actually put it on and see how well it seals
<azonenberg>
If you dont have the facilities for the full osha fit test procedure, there's a trick you can use to get pretty close
<Degi>
Hm maybe I can find a local store. Not like I need it now either lol
<azonenberg>
remove filters, hold your palms over the intake ports, attempt to inhale
<Degi>
Hmm I bet I have omething I can use
<azonenberg>
you shouldn't get any air
<Degi>
Ah yes
<azonenberg>
then hold your hand over the output port, exhale
<azonenberg>
you should feel the mask pressurize and puff up
<azonenberg>
in neither case should there be any hissing or significant air movement
<Degi>
Do inlet ports also have valves?
<azonenberg>
Yes there's check valves on input and output ports
<azonenberg>
among other things this prevents your exhaled droplets from contaminating the filters and growing bacteria in them
<Degi>
Hm can I just spray some stinky stuff around and when it doesnt smell tis hould be ok?
<Degi>
Ah yes
<azonenberg>
Assuming the substance is something your filters will block, yes
<Degi>
Thats probably why my one mask is kinda bad to breathe from lol its probs a year old
<Degi>
(Ik you shouldnt use them more than once...)
<azonenberg>
disposable? yeah
<azonenberg>
if you want to get closer to the official osha fit test procedure what you'll want to do is stand still for a bit, then turn your head side to side for 30 sec, bend your neck up and down for 30 sec, talk for 30 sec, then bend at your waist as far as you can and talk for 30 sec
<azonenberg>
fail if it leaks at any point during that
<azonenberg>
it's only an official fit test result if you use the standard concentrations of the approved testing substances
<azonenberg>
the 3m fit test kit we use has a metered-dose nebulizer and premixed solutions of standard concentrations
<Degi>
Hm it was some FFP3 mask for 3 € per piece
<azonenberg>
so you get a known quantity of aerosol in a hood of known volume
<Degi>
hmm
<azonenberg>
that said, you can get a qualitative result good enough for your own use without that
<Degi>
Oh I can blow up a transistor. That makes a very recognizeable smell
<azonenberg>
yeah but the question is will the filter cartridge block it
<azonenberg>
the main filter categories are particulate (filter) and vapor (activated carbon bed, possibly doped with additives)
<azonenberg>
the filters i'm wearing in that picture are carbon filters for organic vapors doped with acid-neutralizing substances, then a particulate blocking P100 prefilter
<azonenberg>
which makes a good general purpose filter
<azonenberg>
but they're a bit more expensive than ones specialized to only the hazard at hand
<azonenberg>
and also require more effort to breathe through since you're going through more layers
<Degi>
Hmm something that filters aerosolized glass fibers and particulate is probably enough. Solvent vapors would be nice too but I'd probably be too lazy to use it for only that...
<azonenberg>
yeah in that case a particle filter is probably file. those are also the most in demand right now as they also block virus particles :p
<azonenberg>
fine*
<Degi>
oof
<Degi>
Ill just stick some toilet paper into the holes
<lain>
just stay inside forever
<lain>
it's cozy, and safe!
<Degi>
That doesnt help when I vaporize electronics or saw metal...
<lain>
oh :<
<azonenberg>
try not to vaporize them?
<Degi>
Idk sometimes it just happens
<lain>
high volume-per-second air circulation? :3
<Degi>
Hm maybe just get some of those 9 kW watercooled RC motors and attack a prop blade