09:55 <erichvk__> wpwrak, did the email and code make it through the usual spam filters?

09:56 <erichvk__> if not, I can stick them onto some ftp space

12:18 <wpwrak> erichvk__:yes, thanks ! just haven't gotten around to processing it yet

12:32 <erichvk__> np

12:41 <erichvk__> wpwrak, if you are able to suggest any repositories of example files in the meantime, I can do a bit more testing

13:08 <wpwrak> there's a lot of stuff in http://projects.qi-hardware.com/index.php/p/kicad-libs/

13:10 <erichvk__> perfect, thanks. I will test a bit more.

13:38 <erichvk__> wpwrak, geda.c, line 91

13:38 <erichvk__> change

13:38 <erichvk__> fprintf(file, "%d %d ", center.x, -center.y);

13:38 <erichvk__> to

13:39 <erichvk__> fprintf(file, "%d %d ", center.x, center.y);

13:41 <erichvk__> http://imgur.com/a/lybsS

13:41 <erichvk__> seems to be behaving with that one final tweak

13:43 <erichvk__> incidentally, the gEDA PCB fork, pcb-rnd, now can import and export kicad format layouts, and also export .mod files of gEDA footprints in a layout.

14:05 <wpwrak> erichvk__: now checking your mail ... did you get to test the different hole types ? there's some more fun stuff in fped: you can change pad types to make them affect different layers. e.g., normally you have copper + solder mask opening + solder paste. but you can also have pads with just a subset of these

14:06 <wpwrak> e.g., look at qfn.fpd: there, you the center pad has no solder paste. instead, it has little sub-pads on it which only provider solder paste

14:06 <erichvk__> geda pcb only has pins or pads. Pins go through all layers, and I have used default mask and copper clearances. Solder paste is not specified in the footprint.

14:06 <erichvk__> gEDA lets you shrink or grow clearance on a per pad/pin basis

14:07 <erichvk__> and same for mask

14:07 <wpwrak> hmm, how do you do qfns then ? for best performance, they want little solder paste islands, not just one big area

14:08 <erichvk__> gEDA generates a solder mask based on the pad settings, but fabs will often do their own thing with the gerbers

14:08 <wpwrak> i discussed those pads here: http://lists.en.qi-hardware.com/pipermail/discussion/2011-March/007639.html

14:08 <erichvk__> by solder paste I mean stnecil

14:09 <wpwrak> especially the NXP document in [1] is an interesting read

14:09 <wpwrak> poot pcb houses. you make them work hard ;-)

14:09 <wpwrak> pooR, even

14:10 <erichvk__> in gEDA, to achieve the four apperture pad you depict, we'd probably have to merge four pads each with their own solder mask settings

14:11 <erichvk__> the pcb-rnd fork has a new file format in devellopment which is much more flexible

14:12 <erichvk__> my main goal is to get exported geometry of pins, pads, silk working, accepting that things like solder mask, paste, and (x,y) offset holes in pads and slots will not map easily to gEDA

14:13 <wpwrak> (multiple pads) hmm, if you can make the solder mask off-center, then that would work. else, you could try to approximate.

14:14 <erichvk__> four pads in a grid, with marginal overlap, and shrunken paste apertures would provide the effect shown

14:14 <wpwrak> okay, that could work. or add little copper-only filler pads

14:15 <wpwrak> for very "unbalanced" pads, the QFN48 in qfn.fpd are a good example

14:16 <wpwrak> also, there we're at 9 pads for the large center pad

14:17 <wpwrak> in qfn.fpd i used the variables zone_ratio_35 and paste_ratio_20 to calculate the occupation ratios NXP recommend. so it's easy to check how close the design is to that.

14:17 <wpwrak> admittedly, an oddball use of variables ;-)

14:18 <wpwrak> erichvk__: do you work with git ? if you commit your changes in a branch, you could make nice patches from that

14:19 <erichvk__> I never got the sign up email

14:19 <erichvk__> not very capable with git branches

14:20 <wpwrak> also, please don't mix 4 spaces indentation with tab indentation for major levels. major levels are #levels * 1 tab, wrapped lines get an extra four spaces

14:20 <erichvk__> sorry, my bad

14:20 <wpwrak> (mail) hmm, could be part of the mail troubles at the qi-hw server

14:21 <erichvk__> vi pastes spaces instead of tabs, it seems

14:21 <wpwrak> i tried to post something to the qi-hw mailing list on the 24th, but it never made it. says "Temporary local problem". alas, wolfspraul doesn't seem to be around these days

14:22 <wpwrak> i sent a "ping" to the list today, but that still gets the "Temporary local problem"

14:22 <wpwrak> fortunately, the git repo still works :)

14:24 <erichvk__> hehe

14:24 <wpwrak> btw, here is a catalog of "pretty-printed" footprints: http://downloads.qi-hardware.com/people/werner/tmp/kicad-libs-modules.pdf

14:25 <wpwrak> may be useful for finding "interesting" cases with unusual pad configurations and such

14:27 <erichvk__> yeah, p337, qfn 48

14:28 <erichvk__> OK, well that's given me something to think about. For now, hole geometry, sillk, arc line and circle and pad geometry are what 99.9% of gEDA users would be happy with.

14:29 <erichvk__> we will think about how to support the windowing of stencils and solder masks with the new pcb-rnd format

14:40 <wpwrak> for now, maybe fprintf a warning of if the geda dumper gets a layer mix it doesn't know how to handle ?

14:41 <erichvk__> I'm really only familiar with the individual feature export code; is the dump code different?

14:42 <erichvk__> there's nothing wrong with preserving the design intent in the fpd

14:42 <erichvk__> even if not supported by gEDA

14:43 <erichvk__> comments in footprints start with # and are ignored

14:43 <erichvk__> a simple fprintf starting with a # would do the job in the exported footprint

14:46 <wpwrak> yes, i mean what's in geda.c. and i was thinking of fprintf(stderr, ... :) but putting it into the footprint could also be nice, in case you have things further down the pipeline that may want to know

14:48 <erichvk__> I think most gEDA users will be delighted if I announce fairly complete support and link to your hardware library. They won;t be fussed about minor things like paste/mask stuff.

15:07 <erichvk__> and offset holes in pads/pins

15:07 <erichvk__> the mapping is neither surjective nor injective