04:11 <ravelo> Joerg-Neo900: thanks for explaining

04:11 <ravelo> Read it now

08:05 <Joerg-Neo900> juts for correctness: there _are_ situations where you simply can't route stuff - when you need to connect 3 chips of 3*3cm each with traces none longer than 6mm - we don't have any such situation on Neo900

08:06 <Joerg-Neo900> at least not in proto_v2

10:01 <DocScrutinizer05> didn't know I got an alter ego out there: http://www.aptosid.com/index.php?name=PNphpBB2&file=viewtopic&p=18161&sid=ea75004f3c8edfb5154546e87e64f1e6#18161

10:03 <DocScrutinizer05> I'm afraid my experience will be exactly the same

10:25 <Joerg-Neo900> I wonder how >>an sd card holder on the other side of BoB<< is a problem for placing connectors

10:26 <Joerg-Neo900> I mean, neither the B2B conns nor the uSD holder are through-hole components

10:39 <Joerg-Neo900> btw regarding layers needed, we discussed this quite a while ago already, with one of our prospect layouters that then failed to pick up on the task. Seeing the density (ratio of footprints area vs total available area) being very high, they assumed we might need 5 layers instead of 4 for LOWER

10:40 <Joerg-Neo900> actually 6 layers

10:43 <Joerg-Neo900> as a general rule, layouters should start with overprovisioning of layers and try to use as few layers as possible during routing. Then eventually you see how many layers you really need, maybe redo a few details that have a peak in layers needed to reduce layer count there, and as a final step you simply delete the unused layers from PCB config

23:37 <galiven> houkime: http://projects.goldelico.com/p/neo900/timeline/all/ has an atom link, though the most reent entries are July 2017. There's nothing on neo900.org that looks like a bugtracker link to that though.