02:33 <mtrbot-ml> [mattermost] <sb10q> does someone know why a DPSS green laser pointer can get 10s of mW out of a PPKTP doubler crystal that costs $2, whereas every lab setup involves a $$$$$ and finicky enhancement cavity with unobtainium mirrors? is there something special about the 532nm wavelength that makes this exceptionally easy?

04:15 <awygle> whitequark: did nmigen change the name of TSTriple, or the whole approach? doesn't seem to be called that anymore at least

07:49 <_whitenotifier-3> [nmigen] awygle opened issue #315: FSM with transition to nonexistent state should not elaborate - https://git.io/JvmhW

13:33 <mtrbot-ml> [mattermost] <dpn> @sb10q: Nothing magic about 532 nm – the number just tends to crop up because it's the second harmonic of 1064 nm, which you can easily get at high powers from Nd-doped solid-state materials. Regarding unobtainium mirrors vs. cheap laser pointers, it's just a question of conversion efficiency, stability/beam quality, and of course mass manufacturing – it's been a while since <message clipped>

13:34 <mtrbot-ml> [mattermost] <dpn> (NB: By intracavity doubling, the cavity referred to is the cavity of the laser producing the fundamental, not an external enhancement cavity.)

13:40 <mtrbot-ml> [mattermost] <dpn> (And regarding 1064 nm being available in good beam quality at high powers relatively easily, this is very relevant as SHG is a non-linear process; excluding pump depletion/… effects, the doubling *efficiency* goes linear with the input intensity.)

14:20 <mtrbot-ml> [mattermost] <sb10q> there is no intracavity doubling

14:21 <mtrbot-ml> [mattermost] <sb10q> there's a 808nm diode, followed by the Nd crystal (with reflective coatings forming a cavity) followed by the KTP crystal

14:21 <mtrbot-ml> [mattermost] <sb10q> the KTP crystal isn't in any sort of cavity as far as I can tell

14:22 <mtrbot-ml> [mattermost] <sb10q> but I

14:22 <mtrbot-ml> [mattermost] <sb10q> 'm happy to experiment further with it if you think there is one

14:22 <mtrbot-ml> [mattermost] <sb10q> like cutting it in half and see if it still produces green light

17:18 <MikeP> Hey, I'm curious if it's possible to write a Clock Divider in nmigen that uses both positive and negative edges of the sync clock?

17:18 <MikeP> (If I understand the ClockDivisor example in nmigen/examples/basic/arst.py , even a factor of 1 will half the rate of the clock vs sync.)

17:18 <MikeP> (fair to decent chance I'm not understanding that fully though!)

17:27 <MikeP> (In my example I'd naively assumed I could get a 4MHz clock by dividing from my 12MHz clock, but I'm now not sure how)

18:07 <Sarayan> from what I understand, different edges are different clock domains

18:07 <Sarayan> I'm not sure how you turn a signal into a clock domain "generator" TBH

18:09 <whitequark> MikeP: no, and even if you did, it wouldn't really synthesize

18:10 <whitequark> dual edge flip flops are rarely supported and verilog tooling tends to not recognize them either

18:10 <MikeP> For the last 30 mins I've been seeing whether I could get an approach like this to work in nmigen: http://referencedesigner.com/tutorials/verilogexamples/verilog_ex_06.php

18:11 <MikeP> (only in sim right now. Haven't tried to synthesize anything yet)

18:11 <Sarayan> wq, been wondering, say I want to do an oric 1 in nmigen

18:12 <whitequark> one of the goals of nmigen is to avoid having nonsynthesizable constructs

18:12 <Sarayan> that's a 1MHz 6502, 6522 and ay8912, plus a 32MHz ULA that does address decode, video and generates the 1MHz clock

18:12 <MikeP> Doing that first by creating another clock domain that inverts the signal from the first, doing a timer in each CD, then summing the the timers in comb

18:12 <whitequark> and this clock divider, even if you could synthesize it, would be a timing nightmare

18:12 <Sarayan> 6502, 6522, probably even the ay, they need both edges

18:13 <whitequark> you could certainly implement clock.v as written with two clock domains

18:13 <whitequark> but clk_out wouldn't be usable as a clock downstream

18:13 <Sarayan> how is one supposed to do that?

18:13 <whitequark> since it would contain many glitches

18:13 <MikeP> why the timing nightmare? (apologies for the noob question - I have been reading up)

18:13 <whitequark> Sarayan: your case is different

18:13 <whitequark> you have essentially two clocks with a defined phase relationship

18:13 <whitequark> that happen to share a signal

18:14 <whitequark> the case of MikeP is problematic because of this line: assign clk_out = ((pos_count == 2) | (neg_count == 2));

18:14 <Sarayan> ahhh

18:14 <whitequark> in simulation, this combinatorial operation happens instantaneously

18:14 <whitequark> in hardware, not so much

18:14 <whitequark> so you'll get glitches

18:14 <MikeP> ah gotcha

18:14 <Sarayan> the "don't drive the same signal from multiple clock domains" issue?

18:15 <whitequark> the code MikeP linked to doesn't do that

18:15 <MikeP> So is there a sane/safe way to get a 4MHz clock out of a 12MHz base clock?

18:15 <whitequark> pos_count is driven from one domain, neg_count from another

18:15 <whitequark> MikeP: what are you doing specifically with the 4 MHz clock?

18:15 <whitequark> there are a few ways, and the best one depends on your case

18:16 <whitequark> if you just need to slow your logic down 3 times, I suggest using EnableInserter and running your entire circuit on the 12 MHz clock

18:16 <Sarayan> MikeP: what's the problem with clk_out = pos_count < 3 and wrapping at 6?

18:16 <whitequark> (btw, Sarayan, you could also do that; you could run your circuit at 2× the original clock and use pos/neg enable strobes)

18:17 <Sarayan> wq: that would be 32x, but I'd like the keep the sub-components clean, with two clock domains and no hypothesis on what's around

18:18 <whitequark> 32x?

18:18 <MikeP> Right now I'm driving a DAC via SPI and also monitoring that signal from another microcontroller

18:18 <whitequark> oh, ULA

18:18 <Sarayan> yeah. One reason I like nmigen is that it's several orders of magnitude more readable than verilog or vhdl. I'd like to keep it that way :-)

18:19 <whitequark> Sarayan: oh, but you don't have to change it much

18:19 <whitequark> you can give EnableInserter the enables per clock domain

18:20 <whitequark> so rather than having pos/neg domains driven by fclk at different edges,

18:20 <Sarayan> hmmm, I currently have no idea what EnableInserter is

18:20 <whitequark> you would have pos/neg domains driven by fclk*2 with two enables that are out of phase

18:20 <whitequark> most of your code looks exactly the same, only the very toplevel part differs

18:20 <whitequark> ok, so, you know what a DFFE is, vs. a DFF?

18:21 <Sarayan> I know neither of the two acronyms :-)

18:21 <Sarayan> FF = Flip Flop?

18:21 <MikeP> Saryan on "clk_out = pos_count < 3 and wrapping at 6?" - Not sure I fully understand you, but if I only used pos_count, then flipping at 3 "ticks" means a clock division of 6, where I was after a division of 3

18:21 <MikeP> Anyways, I can work around this, and thanks for the help folks.

18:22 <whitequark> MikeP: if you don't need 50% duty cycle specifically you can just have the divided clock active for 2 cycles of original clock out of 3

18:22 <Sarayan> MikeP: you are indeed correct

18:22 <whitequark> whether you need 50% duty cycle depends on what exactly that 4 MHz clock is driving

18:23 <whitequark> if it's some synchronous logic, usually 66% duty cycle would be just fine

18:23 <MikeP> Honestly I think a workaround here is better than sacrificing an assumption of "safer" timing... I imagine I'd end up just digging myself a hole...

18:23 <Sarayan> or, that's 12MHz, not 32. And amusingly the clock is 33% duty cycle

18:24 <Sarayan> or 66, however you count

18:25 <MikeP> I did have a separate piece of code driving the DAC that was able to use an inverted clock domain for setting SPI data before the clock ticked on sync, and that was fine when synthesized. In that case the timing wasn't critical (as long as the data was set sometime before the clock tick) and I was never combining the signals.

18:26 <whitequark> in general you want to avoid having multiple clock domains for as long as possible, it just makes everything nicer

18:26 <MikeP> but was hoping I could generalize that into a clock divider. It's honestly not important for what I'm doing. After a bit I just saw it as a challenge. Letting go now :-)

18:26 <MikeP> Thanks!

18:26 <whitequark> because you never have to think about whether some issue is a logic bug or a CDC error, and there is much less opportunity for sim/synth mismatch

18:34 <_whitenotifier-3> [nmigen] awygle closed issue #315: FSM with transition to nonexistent state should not elaborate - https://git.io/JvmhW