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<Astro->
@sb10q may I declare a hydra jobset for the zc706 project?
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<mtrbot-ml>
[mattermost] <sb10q> sure
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<_whitenotifier-3>
[nmigen-boards] HarryHo90sHK synchronize pull request #38: Option to factor out "clk" from "spi_flash" on Lattice ECP5 - https://git.io/JeFY3
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<lkcl>
whitequark: thank you about the nlnet formal proofs. apologies it never occurred to me to ask you!
<whitequark>
no problem
<lkcl>
i know we talked a while back about the possibility of nlnet funding for nmigen (which is different)
<lkcl>
there's a "set process" for budgets (etc) i'm going through it with ed, on your behalf, so you've not got boring-details-to-go-over
<lkcl>
which is really kind of him to help with.
<lkcl>
there will be other people involved (other people who will want to do "tasks"), however the key value that you provide is: you know what the hell you're doing :)
<lkcl>
others (including me) can go, "ohhh so that's how it's done" and that's incredibly valuable
<lkcl>
whitequark: oh, one very important thing, i started coding again, and ran into a bug involving Cat(*list_of_signals)
<whitequark>
please report an MCVE
<lkcl>
MCVE... yes, i was just about to say i was going to do that :) i remember from last time we talked.
<lkcl>
will let you know how it goes. 23:00 in HK now... will be in touch with it tomorrow
<lkcl>
whitequark: doh. nope. it was a straight silly bug :)
<lkcl>
wark-wark
<whitequark>
that's the good thing about making an MCVE, usually it shows you where the bug was
<whitequark>
whether it's in your code or someone else's
<lkcl>
...because you have to go over every line, working out if it's necessary. nice.
<whitequark>
basically, yes. you wrote most of that code, so you're in a much better position to do it than the maintainers of some upstream library, usually
<whitequark>
it doesn't work well for nondeterministic bugs, or for usability bugs, or for some others. but if it just "doesn't work correctly" then an MCVE is the right choice
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<_whitenotifier-3>
[nmigen] jfng opened issue #312: Assignment to a Record with zero-width fields generates invalid Verilog - https://git.io/Jvtxf
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<_whitenotifier-3>
[nmigen] whitequark commented on issue #312: Assignment to a Record with zero-width fields generates invalid Verilog - https://git.io/Jvtxz
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