00:36 <mtrbot-ml_> [mattermost] <sb10q> it just needs some delay maybe?

02:13 <_whitenotifier-5> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/JvTCO

02:13 <_whitenotifier-5> [m-labs/nmigen] whitequark 7cb3095 - hdl.xfrm: transform drivers as well in DomainRenamer.

02:13 <_whitenotifier-5> [nmigen] whitequark closed issue #304: ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances - https://git.io/JvJWe

02:28 <_whitenotifier-5> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/638242288?utm_source=github_status&utm_medium=notification

02:28 <_whitenotifier-5> [nmigen] Success. 82.17% (+0.07%) compared to e18385b - https://codecov.io/gh/m-labs/nmigen/commit/7cb3095334f7734d15ec9d350043b448c7c5e66d

02:28 <_whitenotifier-5> [nmigen] Success. 100% of diff hit (target 82.09%) - https://codecov.io/gh/m-labs/nmigen/commit/7cb3095334f7734d15ec9d350043b448c7c5e66d

02:31 <_whitenotifier-5> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/638242288?utm_source=github_status&utm_medium=notification

06:14 <_whitenotifier-5> [nmigen-stdio] HarryHo90sHK synchronize pull request #4: serial: A proposal to add verification using formal tools - https://git.io/JexdP

06:26 <_whitenotifier-5> [nmigen-stdio] HarryHo90sHK synchronize pull request #4: serial: A proposal to add verification using formal tools - https://git.io/JexdP

07:59 <_whitenotifier-5> [nmigen-stdio] HarryHo90sHK synchronize pull request #4: serial: A proposal to add verification using formal tools - https://git.io/JexdP

09:41 <zignig> whitequark: I have been battling a off-by-one error on my Boneless for _ages_ as a part of a csr conversion.

09:43 <zignig> ported back to a known old working and it still has it , are you aware of a yosys or nmigen that adds a cycle somewhere ?

09:54 <whitequark> is this in sim or on hardware?

10:19 <spomjaksilp> whitequark (just tagging you bc I often see your nick in the m-lab git repos) your hydra build server seems to have an issue. I encountered http error 500 while nix-channel --update. The website shows "Caught exception in Hydra::Controller::Channel->nixexprs "Can't call method "productnr" on an undefined value at

10:19 <spomjaksilp> /nix/store/lbanazgzsz39sfhvvxwih9609s85r5yz-hydra-2019-08-30/libexec/hydra/lib/Hydra/Controller/Channel.pm line 66, <$read> line 14662.""

10:22 <mtrbot-ml_> [mattermost] <sb10q> spomjaksilp: what's the output of nix-channel --list ?

10:22 <whitequark> I don't use nixos

11:24 <spomjaksilp> mtrbot-ml_ find the output here: https://gist.github.com/spomjaksilp/411f85598702eddfd4f77532a34e5414

11:25 <spomjaksilp> whitequark then nevermind ;)

12:15 <zignig> whitequark: both . sim and hardware.

12:17 <zignig> need to double check my history and branches, but so far it looks like the external bus does not latch the data on the first r_stb strobe.

12:54 <_whitenotifier-5> [nmigen] povauboin commented on issue #304: ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances - https://git.io/JvTwD

13:49 <_whitenotifier-5> [smoltcp] MabezDev commented on issue #323: TcpSocket timeout not respected in SynSent - https://git.io/JvTos

14:31 <_whitenotifier-5> [smoltcp] MabezDev commented on issue #323: TcpSocket timeout not respected in SynSent - https://git.io/JvTKr

15:08 <Astro-> @sb10q I don't think it's delays but fifo levels - which are really to awkward to probe on this peripheral.

15:08 <Astro-> anyway, it's a silver lining on the horizon...

16:32 <miek> whitequark: i was needing ecp5 internal oscillator (OSCG) support in nmigen and found an old IRC log from last year with some advice from you on how to do it. i followed that and came up with this: https://github.com/miek/nmigen/commit/6d380b16f55685ca55dc1a8f30f7b8f6fec9dca0 - does that look reasonable? it works, but i don't really know what i'm doing so i'm not sure if it's correct

16:51 <whitequark> miek: that's almost exactly what I would do myself

16:52 <whitequark> feel free to submit a PR and we'll work out the details

16:52 <miek> great, thanks! i'll do that

17:06 <_whitenotifier-5> [nmigen] miek opened pull request #306: vendor.lattice_ecp5: Support internal oscillator (OSCG) - https://git.io/JvT1i

17:08 <_whitenotifier-5> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/638532040?utm_source=github_status&utm_medium=notification

17:08 <_whitenotifier-5> [nmigen] codecov[bot] commented on pull request #306: vendor.lattice_ecp5: Support internal oscillator (OSCG) - https://git.io/JvT1X

17:08 <_whitenotifier-5> [nmigen] Success. 82.17% remains the same compared to 7cb3095 - https://codecov.io/gh/m-labs/nmigen/compare/7cb3095334f7734d15ec9d350043b448c7c5e66d...d45188662bede6dbf3700f1aa74920e85840dccf

17:08 <_whitenotifier-5> [nmigen] Success. Coverage not affected when comparing 7cb3095...d451886 - https://codecov.io/gh/m-labs/nmigen/compare/7cb3095334f7734d15ec9d350043b448c7c5e66d...d45188662bede6dbf3700f1aa74920e85840dccf

17:08 <_whitenotifier-5> [nmigen] Failure. 82.09% (-0.08%) compared to 7cb3095 - https://codecov.io/gh/m-labs/nmigen/compare/7cb3095334f7734d15ec9d350043b448c7c5e66d...d45188662bede6dbf3700f1aa74920e85840dccf

17:08 <_whitenotifier-5> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/638532040?utm_source=github_status&utm_medium=notification

17:10 <_whitenotifier-5> [nmigen] whitequark reviewed pull request #306 commit - https://git.io/JvT11

17:17 <_whitenotifier-5> [nmigen] miek reviewed pull request #306 commit - https://git.io/JvT1N

17:19 <_whitenotifier-5> [nmigen] whitequark reviewed pull request #306 commit - https://git.io/JvT1x

17:53 <_whitenotifier-5> [nmigen] miek synchronize pull request #306: vendor.lattice_ecp5: Support internal oscillator (OSCG) - https://git.io/JvT1i

17:54 <_whitenotifier-5> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/638549426?utm_source=github_status&utm_medium=notification

17:55 <_whitenotifier-5> [nmigen] Success. 82.17% remains the same compared to 7cb3095 - https://codecov.io/gh/m-labs/nmigen/compare/7cb3095334f7734d15ec9d350043b448c7c5e66d...b261575714b4df9a1f07d9757f2fa9360bb675b5

17:55 <_whitenotifier-5> [nmigen] Success. Coverage not affected when comparing 7cb3095...b261575 - https://codecov.io/gh/m-labs/nmigen/compare/7cb3095334f7734d15ec9d350043b448c7c5e66d...b261575714b4df9a1f07d9757f2fa9360bb675b5

17:55 <_whitenotifier-5> [nmigen] Failure. 82.09% (-0.08%) compared to 7cb3095 - https://codecov.io/gh/m-labs/nmigen/compare/7cb3095334f7734d15ec9d350043b448c7c5e66d...b261575714b4df9a1f07d9757f2fa9360bb675b5

17:55 <_whitenotifier-5> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/638549426?utm_source=github_status&utm_medium=notification

20:30 <_whitenotifier-5> [smoltcp] MabezDev edited a comment on issue #323: TcpSocket timeout not respected in SynSent - https://git.io/JvTKr

20:39 <rjo> another ARTIQ PHY: https://github.com/elhep/FMC_ADC100M_10B_TDC_16cha_gw

21:36 <_whitenotifier-5> [nmigen-boards] nicolas-robin opened pull request #45: Add Digilent Arty Z7-20 board - https://git.io/JvT7N

21:41 <_whitenotifier-5> [nmigen-boards] whitequark reviewed pull request #45 commit - https://git.io/JvT5Y

21:47 <_whitenotifier-5> [nmigen-boards] nicolas-robin reviewed pull request #45 commit - https://git.io/JvT5Z

21:54 <_whitenotifier-5> [m-labs/nmigen-boards] whitequark pushed 1 commit to master [+1/-0/±0] https://git.io/JvT5i

21:54 <_whitenotifier-5> [m-labs/nmigen-boards] nicolas-robin 6fc91b4 - Add Digilent Arty Z7-20 board.

21:54 <_whitenotifier-5> [nmigen-boards] whitequark closed pull request #45: Add Digilent Arty Z7-20 board - https://git.io/JvT7N

21:54 <_whitenotifier-5> [nmigen-boards] whitequark commented on pull request #45: Add Digilent Arty Z7-20 board - https://git.io/JvT5P