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[nmigen] JarrettBillingsley commented on issue #289: Finding out what resources an nMigen module uses in the output design - https://git.io/JeAxH
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[nmigen] JarrettBillingsley closed issue #289: Finding out what resources an nMigen module uses in the output design - https://git.io/JeA7j
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[nmigen] whitequark commented on issue #289: Finding out what resources an nMigen module uses in the output design - https://git.io/JeAp4
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[nmigen] JarrettBillingsley commented on issue #289: Finding out what resources an nMigen module uses in the output design - https://git.io/JeApw
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[nmigen] daveshah1 commented on issue #289: Finding out what resources an nMigen module uses in the output design - https://git.io/JexvF
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[nmigen] whitequark commented on issue #289: Finding out what resources an nMigen module uses in the output design - https://git.io/JexvA
<Sarayan>
whitequark, around? you seem to be active
<whitequark>
Sarayan: sure
<Sarayan>
You who knows how to find anything and everything, do you have any idea how hdmi vrr (variable refresh rate) works, and whether it can be used with an adv7513 as the hdmi tx?
<Sarayan>
e.g. whether one could use vrr for emulation on the fpga of a terasic de10-nano
<Sarayan>
the mister standard fpga board
<whitequark>
i haven't heard of vrr before but it looks like it's the standard version of gsync/freesync
<whitequark>
what do you want to do exactly?
<Sarayan>
see if when I get a de10 I can run the vsync at the real rate of the emulated system on my next tv that should have vrr
<Sarayan>
(yeah, that means I don't have the tv or the de10 yet, but heh :-)
<whitequark>
oh i see
<Sarayan>
I'm already working on being able to run yosis/nextpnr for that cyclone too, by RE-ing quartus
<Sarayan>
and it's going amusingly well, lldb/python is fun
<daveshah>
Have you spoken to ZirconiumX? they are working on RE of that cyclone too
<ZirconiumX>
Oh, hey Sarayan
<Sarayan>
daveshah: yeah, and I really hope to be able to give him a lot of information he's missing
<whitequark>
and i don't know nearly enough about hdmi to guess. in fact i know very little about it.
<ZirconiumX>
Also wouldn't variable refresh be hell when you've got fixed PLLs?
<whitequark>
ZirconiumX: that's why adaptive sync (so far) involved shipping a huge FPGA in the display itself
<Sarayan>
it's not so much variable as non-standard
<ZirconiumX>
The problem itself exists just fine in the standard
<Sarayan>
wq: let me know if you happen to see it leaking :-)
<daveshah>
My guess would be that VRR requires some data to be sent in the aux data packets
<daveshah>
(during blanking)
<daveshah>
if the ADV7513 doesn't let you send arbitrary data in those packets then I doubt VRR is possible
<daveshah>
but I haven't actually checked the docs for that
<whitequark>
Sarayan: I've got 2.0 (a, not b)
<ZirconiumX>
HDMI ties resolution and framerate to the TMS clock, so changing resolution and framerate both need to change the TMS clock
<daveshah>
Not if you have a high TMS clock and change the blanking
<ZirconiumX>
The ADV7513 is a pretty capable chip, actually. It's kinda surprising.
<whitequark>
HDMI 2.1 doesn't even have TMDS clock
<whitequark>
(afaik)
<whitequark>
it's now packet based like DP
<Sarayan>
the adv is supposed to be 1.4
<Sarayan>
but I don't know the differences between 1.4 and 2.x
<Sarayan>
especially if you're not going over full hd
<ZirconiumX>
daveshah: I hadn't actually considered that approach to dynamic resolution, but if the TV can cope with really long blanking it would work nicely
<daveshah>
I have a feeling that there are some 30Hz modes that are 60Hz pixel clocks with loads of blanking
<ZirconiumX>
Yeah. but the ADV7513 is the chip on the DE-10 Nano
<ZirconiumX>
So this isn't particularly relevant as such
<ZirconiumX>
We already know Terasic get chips on the cheap because they're the main manufacturer of Cyclone dev boards
<key2>
ah i didnt read, i thought u were looking for a chip
<ZirconiumX>
Also the ADV7513 is a plenty capable chip, actually
<ZirconiumX>
It can do things like 4:2:2 YCbCr colour space conversion
<ZirconiumX>
I don't particularly *need* that for my particular goal, but still
<Sarayan>
the de-10 nano has the advantages of existing and not being too expensive for its power
<Sarayan>
I'm not sure that for emulation there's currently something better within the same kind of budget
<ZirconiumX>
Also the MiSTer community has a lot of stuff for it
<Sarayan>
Yup, but that's less important, at least for me
<Sarayan>
building the stuff is most of my fun :-)
<ZirconiumX>
I mean, I'm the nmigen-boards DE10NanoPlatform maintainer :P
<Sarayan>
cool, that's gonna be useful
<Sarayan>
I hope to be able to do everything in nmigen
<Sarayan>
I find verilog really annoying the read
<Sarayan>
to
<whitequark>
\o/
<ZirconiumX>
I find Verilog really annoying to write
<ZirconiumX>
:P
<Sarayan>
yeah, that too
<Sarayan>
did some vhdl ages ago, it was less bad
<whitequark>
don't get me started on the Verilog specification
<Sarayan>
but nmigen is better than both
<whitequark>
it is extraordinarily annoying to implement
<Sarayan>
wq: can nmigen be used to build something (oric1 sim) where the global clock is 32MHz and used for the video generator, but that generator divides it down to 1MHz and that's what is used for the 6502, 6522 and others?
<whitequark>
oric1?
<Sarayan>
yeah, an old computer I still have in a box somewhere
<Sarayan>
relatively simple, the video ula + 6502, 6522 and ay8192
<whitequark>
oh gotcha
<Sarayan>
feels like a good start system to me
<whitequark>
sure, why not
<whitequark>
do you want to do a multi clock domain system or a fully synchronous?
<whitequark>
I'm thinking the latter would be less headache
<Sarayan>
I have no idea what's the best idea
<Sarayan>
I'm sure I don't want the 6502/6522/etc to know anything about how their 1MHz clock is generated
<Sarayan>
so that they're reusable
<ZirconiumX>
Meanwhile, I'm trying to write an unnecessarily-generic multi-write-port RAM to work around memory_bram being pathologically bad in that scenario
<whitequark>
oh sure, you'll just do EnableInserter(stb, Your6502Core()), and then stb would be high exactly 1 cycle out of 32
<whitequark>
EnableInserter(stb)(Your6502Core()) rather
<Sarayan>
I have no idea what you mean, but I'll ask again once I do have the 6502, 6522, etc working :-)
<Sarayan>
plus I don't have a de10 yet, so it's not as if I could really test anything
<whitequark>
tl;dr 6502 won't know anything and will be perfectly reusable
<whitequark>
re de10: I could probably grab mine and give you an ssh to it
<whitequark>
ssh tunnel
<whitequark>
oh, wait, I have a de0
<Sarayan>
well, lemme finish learning nmigen with the 6522 and extracting everything out of quartus. I'm kinda slow, so let's take our time :-)
<ZirconiumX>
~~I left my DE10 at uni~~
<whitequark>
sure
<Sarayan>
I finished uni in 1999 ;-)
* Sarayan
<- old fool
<ZirconiumX>
~~I was born in 1999~~
<ZirconiumX>
Actually, thinking about it, even if I gave you SSH access for the DE10 that I don't currently have, you'd have to hack around the FPGA->ARM bridge not being implemented at present
<Sarayan>
yeah
<Sarayan>
that could get complicated fast :-)
<ZirconiumX>
I think WQ mentioned something about an InstancePin to handle pins that are only available via an instance
<ZirconiumX>
Which I think the bridge comes under
<whitequark>
yes, the case of requesting a resource that is not attached to a pin is admittedly something i haven't anticipated
<whitequark>
so it'll require minor rework of the platform layer
<ZirconiumX>
nmigen.back.verilog.YosysError: ERROR: Assert `switch_it->signal.size() == compare_it.size()' failed in kernel/rtlil.cc:1420.
<ZirconiumX>
Hurray, I broke Yosys
<ZirconiumX>
...This is going to be a pain to bugpoint, actually.
<ZirconiumX>
Because I need to be able to read the IL in to bugpoint it
<whitequark>
I would start by scrolling through the file
<ZirconiumX>
Should I just send you the nMigen? It's not very big.
<whitequark>
sure, i can take a look
<whitequark>
hm, not the IL?
<whitequark>
oh right, you use quartus, nmigen doesn't dump IL before Verilog there
<whitequark>
you have to add an intermediate signal
<whitequark>
the error sucks though, so you can file an issue about that
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[nmigen] ZirconiumX opened issue #290: Unclear error message when using an Array as port - https://git.io/Jexq6
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[nmigen] JarrettBillingsley commented on issue #289: Finding out what resources an nMigen module uses in the output design - https://git.io/JexYt
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[nmigen] whitequark commented on issue #289: Finding out what resources an nMigen module uses in the output design - https://git.io/JexY0
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[nmigen] JarrettBillingsley commented on issue #289: Finding out what resources an nMigen module uses in the output design - https://git.io/JexYV
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[nmigen] whitequark commented on issue #289: Finding out what resources an nMigen module uses in the output design - https://git.io/JexY5
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[nmigen] JarrettBillingsley commented on issue #289: Finding out what resources an nMigen module uses in the output design - https://git.io/JexYd
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[nmigen] JarrettBillingsley opened issue #291: Need a way to attach attributes to memories - https://git.io/JexYF
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[nmigen-stdio] jfng opened pull request #3: serial: fixes, more tests and docstrings. - https://git.io/Jex3M