07:40 <GitHub150> [artiq] sbourdeauducq pushed 2 new commits to rtio-sed: https://github.com/m-labs/artiq/compare/490c9815a295...3c922463a0d4

07:40 <GitHub150> artiq/rtio-sed 3c92246 Sebastien Bourdeauducq: style

07:40 <GitHub150> artiq/rtio-sed 8e5ab90 Sebastien Bourdeauducq: rtio/sed: add FIFO wrapper

10:10 <_florent_> rjo: yes I'll implement the hardware changes, I need to test lower bitstream before sending it to greg, will do today or on next monday

11:20 <rjo> _florent_: ack

13:08 <d_n|a> rjo: Thanks – that actually doesn't sound too terrible, even with, say, 16 ns extra for the clock domain crossings. Of course, it's still a very non-trivial undertaking to implement this – buying 40 long SMA cables is easier for now ;)

13:14 <rjo> d_n|a: even running the current LVDS over ~10m might be possible. 2 novogorny on one long VHDCI cable. someone should test the limit.

18:04 <hartytp> d_n|a: if you want to try that out with the VHDCI_carrier, there is a 5m VHDCI cable in my lab you're welcome to borrow.

20:11 <Arpit> >> maybe the best way would be to implement a differential tristate << I have went code related to SPI (in artiq) and tri state (in migen). But I couldn't figure out lots of things in just few hours of code browsing. Though I read artiq documentation and migen documentation (present in the file "fhdl.rst"), many things are not yet clear to me. One of the things is, if gateware/spi.py calls cs_n_t.o.eq in comb, how does that affect volt

20:12 <Arpit> (target pin)? What is the path in source code that links function call cs_n_t.o.eq to voltage on pin pads.cs_n (target pin)? Also, if you could give an outline on how to implement a differential tristate, it'd help.

21:49 <GitHub114> [smoltcp] steffengy opened pull request #43: [WIP] hardware based checksum generation & validation (master...master) https://git.io/v55Ck

22:07 <GitHub144> [smoltcp] steffengy commented on issue #43: @whitequark ... https://git.io/v55lf