sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> whitequark, when does smoltcp iface.poll return Error::Exhausted, and why should it handled like no error occured?
<sb0> *be handled
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<sb0> rjo, how do you simulate a 3d trap with electrode?
<sb0> ha, I was looking at nist-ionstorage/electrode
<rjo> uses both.
<sb0> for axial confinement with DC, why does this need high voltages at all?
<sb0> (with a quadrupole trap + two dc endcaps)
<rjo> sb0: how is that RGMII work coming along?
<whitequark> sb0: not anymore it should not be ignored
<whitequark> it means you're out of buffer space somewhere
<sb0> _florent_, do you want me to write (but not debug if the hardware acts up in some strange way) the rust clock programming code?
<_florent_> sb0: if you have time yes that would help me
<_florent_> sb0: I can test it and debug, no problem
<sb0> _florent_, I'm more than happy to do that if you get the rgmii to work :)
<_florent_> sb0: yes why not, but what converter do I need to be able to test rgmii?
<sb0> IIRC Greg has sent you a cable with SATA/SFP?
<sb0> GbE switches can also be used, though they typically won't let you run wireshark/tcpdump on the port directly
<sb0> whitequark, okay, so I can just panic on error (e.g. use .expect())
<sb0> so, Greg has finally received the RTM board yesterday, and is debugging
<whitequark> sb0: no
<whitequark> in general, errors returned by .poll() should be logged and ignored
<whitequark> if you don't have a log, then just ignored
<sb0> _florent_, how are the hmc register values determined? from the ADI windows tool?
<GitHub62> [ionpak] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/ionpak/commit/916e9407803b402c144b2d81560954c2b6101649
<GitHub62> ionpak/master 916e940 Sebastien Bourdeauducq: update smoltcp
<GitHub104> [artiq] sbourdeauducq commented on issue #827: Your misoc version does not match the one prescribed in the artiq-dev recipe. https://github.com/m-labs/artiq/issues/827#issuecomment-326643407
<_florent_> sb0: for the hmc7043, from the gui
<_florent_> sb0: the gui generates python files like this https://github.com/enjoy-digital/sayma_test/blob/master/doc/hmc7043_config_10gbps.py
<_florent_> sb0: for the hmc830, it's from examples find in the gui configurator, but we need to at least understand some of the configuration to get pll lock, be sure vco is in the right range, etc...
<_florent_> sb0: for now I was doing that manually with the scope
<GitHub43> [sinara] gkasprow pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/970bce015e3a7b4aa89621be5a7d451671d441b4
<GitHub43> sinara/master 970bce0 Greg: added pdfs with variants
<sb0> python is quite a weird format to export this
<GitHub85> [sinara] gkasprow pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/36accefc7b4795b659c620a986389523c383a57c
<GitHub85> sinara/master 36accef Greg: panels update
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<sb0> hm, lots of speculation in there
<whitequark> oh, you don't know
<whitequark> there's an entire history of fringe theory of axonal signal conduction, like there was one that said it was actually phonons, and another that said it was actually heat
<whitequark> and the measurable electrical potentials are just a side effect
<whitequark> they're very entertaining
<whitequark> it's like reading those papers that prove that time travel is not prohibited by GR
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<GitHub153> [sinara] marmeladapk pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/5b273cb78c434a9e459bb5610a499147142e5daf
<GitHub153> sinara/master 5b273cb Paweł Kulik: Kasli...
<sb0> _florent_, https://hastebin.com/onulojejud.py << no need to parse things yourself...
<_florent_> sb0: yes thanks, I was aware of that (rjo did the same)
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<GitHub50> [artiq] sbourdeauducq pushed 2 new commits to sinara: https://github.com/m-labs/artiq/compare/c5fe2799cf4c...4baf17cebe94
<GitHub50> artiq/sinara 4baf17c Sebastien Bourdeauducq: libboard: generate HMC7043 register write list
<GitHub50> artiq/sinara 091bb28 Sebastien Bourdeauducq: libboard: use libbuild_artiq
<sb0> fpga clock: 250MHz (div=4) << shouldn't it be 125MHz?
<sb0> is this the rtio clock?
<sb0> if the whole thing could run at 250 including drtio then great, but I rather assume that "ultrascale" is 95% marketing blah blah
<sb0> _florent_, self.regs.hmc_spi_xfer.write(0b01 | 32*WRITE_LENGTH) << what is 0b01?
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<_florent_> sb0: the 250MHz clock is probably for the jesd transceiver
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<_florent_> sb0: 0b01 is the chip select IIRC
<_florent_> sb0: I ordered a TP-LINK MC220L media converter, I'll have it in 1/2 days
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<sb0> _florent_, then there's a problem, both 830 and 7043 have the same CS
<sb0> _florent_, excellent, thanks!
<_florent_> sb0: indeed, I managed this externally, could be better: https://github.com/enjoy-digital/sayma_test/blob/master/sayma_rtm.py#L19
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<sb0> whitequark, how is the TCP fixing coming along?
<GitHub82> [smoltcp] whitequark pushed 1 new commit to master: https://git.io/v52BX
<GitHub82> smoltcp/master 550deb3 whitequark: Don't instantly ACK every received TCP segment....
<travis-ci> m-labs/smoltcp#208 (master - 550deb3 : whitequark): The build passed.