sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<sb0> _florent_, https://github.com/enjoy-digital/sayma_test/blob/master/sayma_rtm.py#L195-L201 << yes, I don't get how that code works
<GitHub153> [artiq] sbourdeauducq pushed 1 new commit to sinara: https://github.com/m-labs/artiq/commit/33f053cff8f3ef9f1f27c890071a95924fad9742
<GitHub153> artiq/sinara 33f053c Sebastien Bourdeauducq: libboard: complete but undebugged support for HMC830/7043 programming
<GitHub11> [misoc] sbourdeauducq pushed 1 new commit to master: https://git.io/v526M
<GitHub11> misoc/master 7d9e605 Sebastien Bourdeauducq: cpu_interface: disable Rust warning for unused read_volatile/write_volatile imports...
<bb-m-labs> build #249 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/249
<sb0> bb-m-labs, force build --branch=sinara artiq
<bb-m-labs> build forced [ETA 32m18s]
<bb-m-labs> I'll give a shout when the build finishes
<GitHub186> [artiq] sbourdeauducq pushed 2 new commits to sinara: https://github.com/m-labs/artiq/compare/33f053cff8f3...34ec37ac8533
<GitHub186> artiq/sinara 34ec37a Sebastien Bourdeauducq: conda: bump misoc
<GitHub186> artiq/sinara 2b2b345 Sebastien Bourdeauducq: firmware: wait for serwb to be ready before proceeding further
<GitHub61> [misoc] sbourdeauducq pushed 1 new commit to master: https://git.io/v526h
<GitHub61> misoc/master 6abc1b4 Sebastien Bourdeauducq: conda: sanitize version
<GitHub100> [migen] sbourdeauducq pushed 1 new commit to master: https://git.io/v52ie
<GitHub100> migen/master 1a145a5 Sebastien Bourdeauducq: conda: sanitize version
<sb0> ysionneau, was it you who started this py_<git commit count> conda version syntax?
<bb-m-labs> build #250 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/250
<bb-m-labs> build #187 of migen is complete: Failure [failed conda_build conda_remove] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/187 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<GitHub25> [migen] sbourdeauducq pushed 1 new commit to master: https://git.io/v52iw
<GitHub25> migen/master 1ccf140 Sebastien Bourdeauducq: conda: use new noarch system
<sb0> hm, I'm actually not sure if it should be py_ or py35_
<bb-m-labs> build #188 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/188
<bb-m-labs> build #767 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/767
<sb0> "The version limit for your license is '2017.08' and will expire in -6 days"
<sb0> xilinx can't even get messages like that right
<sb0> no wonder things that are more complicated, like clock constraints or transceivers, suck halfway to the moon
<bb-m-labs> build #564 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/564
<bb-m-labs> build #1667 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1667
<sb0> _florent_, also the bridge causes clock routing to fail
<sb0> this "IBUFDS" is for serwb_phy_clk_i
<sb0> why is the ultrascale _receiving_ the clock?
<_florent_> sb0: for the IBUFDS, it should be master here instead of slave
<_florent_> sb0: probably a merge issue, I can't fix now, but will do later
<ysionneau> sb0: nop
<GitHub73> [artiq] enjoy-digital pushed 1 new commit to sinara: https://github.com/m-labs/artiq/commit/2091c7696a24f5468a81ce4d6b74841d89fbcba0
<GitHub73> artiq/sinara 2091c76 Florent Kermarrec: artiq/gateware/targets/sayma_amc_standalone: fix serwb_pll vco_div and serwb_phy mode
rohitksingh_work has joined #m-labs
<GitHub170> [artiq] jordens commented on issue #778: Funded by Oxford, for local RTIO and DRTIO, DRTIO trees and Kasli Repeater and Master modes, outputs only.... https://github.com/m-labs/artiq/issues/778#issuecomment-327424876
<GitHub21> [artiq] jordens commented on issue #778: Funded by Oxford, for local RTIO and DRTIO, DRTIO trees and Kasli Repeater and Master modes, outputs only.... https://github.com/m-labs/artiq/issues/778#issuecomment-327424876
<GitHub21> [artiq] sbourdeauducq commented on issue #778: Let me just write that code first, I need to do some experimentation e.g. with the FIFO selector, then it can be documented. https://github.com/m-labs/artiq/issues/778#issuecomment-327444191
<sb0> _florent_, okay it compiles now. thanks!
<GitHub109> [artiq] sbourdeauducq pushed 3 new commits to master: https://github.com/m-labs/artiq/compare/74b7010d676c...629827f573cb
<GitHub109> artiq/master 7fe5d73 Sebastien Bourdeauducq: conda: bump migen/misoc
<GitHub109> artiq/master 264d5fd Sebastien Bourdeauducq: runtime: fix Rust types in RTIO...
<GitHub109> artiq/master 629827f Sebastien Bourdeauducq: doc/slides: minor fixes
<bb-m-labs> build #768 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/768
<bb-m-labs> build #565 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/565
<bb-m-labs> build #1668 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1668
rohitksingh_wor1 has joined #m-labs
rohitksingh_work has quit [Ping timeout: 240 seconds]
rohitksingh_wor1 has quit [Read error: Connection reset by peer]
Gurty has quit [Ping timeout: 252 seconds]
rohitksingh has joined #m-labs
Gurty has joined #m-labs
<rjo> _florent_: is that observation correct that this is the first time we have (partial) CGS?
<GitHub171> [artiq] jbqubit commented on issue #778: Splendid! This will help Sayma RTIO and DSP modulation. https://github.com/m-labs/artiq/issues/778#issuecomment-327518954
mumptai has joined #m-labs
<_florent_> rjo: no, I'm able to get CGS and ILAs, good checksum etc... but we loose sync just after
<rjo> ok. but i have never seen it in ay printouts from those scripts.
<rjo> maybe we have power supply issues?
<larsc> receiver?
<rjo> _florent_: if you are getting that number of errors, i'd expect it to complain and unsync. maybe we should try to get it going with four lanes first (you seemed to be able to get four lanes of PRBS working) while greg circles over the hardware.
<rjo> _florent_: if we get that going, we can already integrate the rest.
<rjo> larsc: i'd think a locked and synced DAC uses more power than an unlocked one. maybe the power supply can't cope.
<larsc> rjo: so FPGA->DAC?
<rjo> larsc: yes
<rjo> larsc: would it loos sync after succeeding CGS and ILA if one lane is marginal signal quality and causes a few errors?
<rjo> *loose
<larsc> I've seen these resync cycles before
<larsc> but I don't know exactly what caused them
<rjo> hmmm
<larsc> but I believe it is related to the alignment of the LMFCs
<rjo> w.r.t each other or w.r.t. sysref?
<larsc> with each other
<GitHub195> [artiq] arpitagrawal23 commented on issue #827: Hi @sbourdeauducq ... https://github.com/m-labs/artiq/issues/827#issuecomment-327557306
rohitksingh has quit [Quit: Leaving.]
<GitHub78> [artiq] jordens commented on issue #827: @arpitagrawal23 can you reproduce that (please try)? Or is it just because your enviroonment got out of sync with the working tree? https://github.com/m-labs/artiq/issues/827#issuecomment-327566482
<GitHub182> [artiq] jordens commented on issue #827: @arpitagrawal23 can you reproduce that (please try)? Or is it just because your environment got out of sync with the working tree? https://github.com/m-labs/artiq/issues/827#issuecomment-327566482
<GitHub17> [artiq] arpitagrawal23 commented on issue #827: Hi @jordens ... https://github.com/m-labs/artiq/issues/827#issuecomment-327568725
<GitHub184> [artiq] jordens commented on issue #827: I am not referring to the top post, but to your analysis. When doing what you said you did, which misoc version does it install? And which one is in `artiq-dev/meta.yaml`?... https://github.com/m-labs/artiq/issues/827#issuecomment-327573761
<GitHub81> [artiq] arpitagrawal23 commented on issue #827: It installed misoc version 0.6.dev py_64+git7d9e6057 but artiq-dev/meta.yaml file mentions misoc version as 0.6.dev py_35+gitd6f86c03. https://github.com/m-labs/artiq/issues/827#issuecomment-327585039
<GitHub164> [artiq] jordens created @head from master (+0 new commits): https://github.com/m-labs/artiq/commits/@head
<GitHub16> [artiq] jordens deleted @head at 629827f: https://github.com/m-labs/artiq/commit/629827f
<GitHub68> [artiq] jordens commented on issue #827: No, [it doesn't](https://github.com/m-labs/artiq/blob/7fe5d73/conda/artiq-dev/meta.yaml#L18). You said you "cloned the artiq git repo". https://github.com/m-labs/artiq/issues/827#issuecomment-327588369
<GitHub107> [artiq] arpitagrawal23 commented on issue #827: Actually I had done that at on 9/1 at 15:16 EST, right after @sbourdeauducq had commented on this thread. Had also taken a picture which shows that all modules were downloaded from the internet (and not taken from system's cache).... https://github.com/m-labs/artiq/issues/827#issuecomment-327590434
<GitHub6> [artiq] jordens commented on issue #827: Come on. Nobody can help you if you don't take the questions seriously. Can you reproduce it **now** and using **the steps you listed**? Anything else is less than helpful.... https://github.com/m-labs/artiq/issues/827#issuecomment-327593393
<GitHub171> [artiq] arpitagrawal23 commented on issue #827: Apologies for that. But actually I didn't need any help on this topic. My setup started working fine after explicitly installing the right misoc version by giving conda install command (mentioned in my earlier comments). I just wanted to report that conda env create command is not honouring git hash mentioned in conda/artiq-dev/meta.yaml file and if someone think that it is a valid issue, then it sh
mumptai has quit [Quit: Verlassend]
<GitHub72> [artiq] sbourdeauducq commented on issue #827: > I just wanted to report that conda env create command is not honouring git hash mentioned in conda/artiq-dev/meta.yaml file... https://github.com/m-labs/artiq/issues/827#issuecomment-327638764