sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> rjo, are you using the kc705s?
<sb0> assuming not. terminating your flterm...
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<GitHub> [artiq] sbourdeauducq pushed 3 new commits to master: https://github.com/m-labs/artiq/compare/bd55436668bb...7e8348a73e4b
<GitHub> artiq/master 59e7967 Sebastien Bourdeauducq: satman: program Si5324 BWSEL depending on frequency
<GitHub> artiq/master 7e8348a Sebastien Bourdeauducq: si5324: fix error handling
<GitHub> artiq/master 0bfce37 Sebastien Bourdeauducq: satman: do not use Si5324 automatic clock switching...
<bb-m-labs> build #406 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/406
<bb-m-labs> build #1323 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1323 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<sb0> the si5324 is another pain in the ass
<sb0> takes forever to lock (up to 10 seconds), switching clocks by writing the register does not immediately clear the lock indicator
<sb0> how is it even possible to know that the clock switch has completed and it's locked to the new clock? I cannot think of a way to do it that doesn't have races or other potential intermittent problems
<sb0> other than waiting the full 10 seconds and checking the lock indicator...
<sb0> sigh, proprietary chips
<cr1901_modern> The older I get, the less patience I have for proprietary *anything*
<cr1901_modern> a PLL taking 10 seconds to lock up sounds very odd to me, btw
<cr1901_modern> is it more than one chip exhibiting that?
<sb0> the loop bandwidth is very low, so there's an excuse for that
<cr1901_modern> Okay, cool (and I assume you need the loop bandwidth that low for your application to prevent jitter)
<sb0> i'll have to see if we can increase the loop bandwidth
<sb0> the 5324 has some "fast lock" features that temporarily increases the loop bandwidth while it's locking, but this does not seem to work very well
<cr1901_modern> "switching clocks by writing the register does not immediately clear the lock indicator" <-- prob is so slow to detect changes that it actually takes that long to lose lock :P?
<sb0> something like that, either way it's annoying
<GitHub> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/9501d37378f2998bc250edd71de55526d2ee624c
<GitHub> artiq/master 9501d37 Sebastien Bourdeauducq: firmware: wait longer for Si5324 lock + more monitoring
<sb0> "Lock time would normally be much longer for a low loop BW setting, such as 4 Hz, and on the order of several seconds to minutes"
<sb0> *minutes*
<cr1901_modern> Where'd you read this?
<cr1901_modern> Oh ffs...
<cr1901_modern> Loss-of-Lock (LOL) indeed
<cr1901_modern> Now I want to know how the Loss-of-Lock logic works. If I'm reading this app note correctly, when the fast-lock feature is used, the LOL alarm doesn't actually reflect the true lock time.
<cr1901_modern> The "naive" way of measuring whether a loop has lock or not is to monitor the derivative of the phase difference. If the si5324 were doing that, the LOL flag should've been unset in ~1 second if going by figure 5
<cr1901_modern> Oh. I see. The LOL time is basically a crapshoot, according to page 5.
<bb-m-labs> build #407 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/407
<bb-m-labs> build #1324 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1324 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<rjo> sb0: ok. you can generally terminate it if i don't reply within five minutes.
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<GitHub> [artiq] sbourdeauducq commented on issue #562: @cjbe Basic DRTIO with outputs only works at 1.25Gbps with commit 9501d37378f2998bc250edd71de55526d2ee624c. You can have a look if you want. https://github.com/m-labs/artiq/issues/562#issuecomment-280840408
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<GitHub> [artiq] jordens pushed 4 new commits to master: https://github.com/m-labs/artiq/compare/9501d37378f2...bc3fc26e3489
<GitHub> artiq/master 3e2dad6 Robert Jordens: misoc: bump (mor1kx pcu)
<GitHub> artiq/master 6b5b679 Robert Jordens: libboard: PCU regs
<GitHub> artiq/master c022b53 Robert Jordens: kernel_cpu: enable perf counters
<GitHub> [artiq] jordens pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/bc3fc26e3489...751940885784
<GitHub> artiq/master 7519408 Robert Jordens: coreanalyzer: add SPIMaster support
<GitHub> artiq/master 41e8acf Robert Jordens: coreanalyzer handle input events without timestamp...
<GitHub> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/039ced6637db23bc37dbc20c8cd79f6a12ff9066
<GitHub> artiq/master 039ced6 Robert Jordens: coreanalyzer: use VCD scopes for DDS/SPI
<bb-m-labs> build #408 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/408
<bb-m-labs> build #1325 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1325 blamelist: Robert Jordens <rj@m-labs.hk>
<GitHub> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/1573ff5fc11f48fb39770e1a434253c9d4d3ed29
<GitHub> artiq/master 1573ff5 Robert Jordens: coreanalyzer: add WB stb signal
<GitHub> [artiq] jordens commented on issue #672: @dleibrandt thanks.... https://github.com/m-labs/artiq/issues/672#issuecomment-280847030
<bb-m-labs> build #409 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/409
<bb-m-labs> build #1326 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1326 blamelist: Robert Jordens <rj@m-labs.hk>
<bb-m-labs> build #410 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/410
<bb-m-labs> build #1327 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1327 blamelist: Robert Jordens <rj@m-labs.hk>
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