sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub> [artiq] cjbe opened pull request #668: Add experiment repository to experiment PYTHONPATH (master...repo_absolute_imports) https://github.com/m-labs/artiq/pull/668
<sb0> I'm also against that, especially as the gateware also tends to change (drtio, dma etc.)
<sb0> it adds more friction to every such change
<sb0> if we had one more person to take care of updating the emulator then OK, but we don't
<GitHub> [artiq] sbourdeauducq commented on issue #668: Problems with artiq_run, and now with artiq_browser and potential misbehavior when the repository directory is not in an empty directory... are you sure relative imports are not better? https://github.com/m-labs/artiq/pull/668#issuecomment-277406700
cr1901_modern has quit [Ping timeout: 255 seconds]
<sb0> we should write nice datasheets/manuals for the sinara hardware. I'm happy to do that.
cr1901_modern has joined #m-labs
GitHub77 has joined #m-labs
GitHub77 has left #m-labs [#m-labs]
<GitHub77> si5324_test/master 9e11ec8 Sebastien Bourdeauducq: move gateware implementation to subfolder
<GitHub77> si5324_test/master 4c19e0f Sebastien Bourdeauducq: resurrect firmware implementation
<GitHub77> si5324_test/master 009d65c Sebastien Bourdeauducq: cleanup
<GitHub77> [si5324_test] sbourdeauducq pushed 3 new commits to master: https://github.com/m-labs/si5324_test/compare/9662c9222504...4c19e0f39d9f
GitHub135 has joined #m-labs
GitHub135 has left #m-labs [#m-labs]
<GitHub135> si5324_test/master edf03b6 Sebastien Bourdeauducq: update to current MiSoC
<GitHub135> [si5324_test] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/si5324_test/commit/edf03b6eb054efa8f798e7dfe83960225daedc9e
<GitHub108> [misoc] whitequark pushed 1 new commit to master: https://git.io/vDny9
<GitHub108> misoc/master 4cb4cf2 whitequark: software: make it more convenient to use other cargo actions.
<bb-m-labs> build #202 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/202
sb0 has quit [Quit: Leaving]
kuldeep_ has quit [Read error: Connection reset by peer]
sandeepkr_ has quit [Remote host closed the connection]
kuldeep_ has joined #m-labs
sandeepkr_ has joined #m-labs
hedgeberg is now known as hedgeberg|away
sb0 has joined #m-labs
sb0 has quit [Client Quit]
sb0 has joined #m-labs
GitHub50 has joined #m-labs
<GitHub50> si5324_test/master 0d06306 Sebastien Bourdeauducq: use same SMA connections as ARTIQ DRTIO
GitHub50 has left #m-labs [#m-labs]
<GitHub50> si5324_test/master 8ac1a61 Sebastien Bourdeauducq: remove build scripts...
<GitHub50> [si5324_test] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/si5324_test/compare/edf03b6eb054...0d06306cfdd4
<GitHub> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/c39394b4d5f800cdc3fd524c17ad589c3f3f3097
<GitHub> artiq/master c39394b whitequark: firmware: port the exception handling routines to Rust.
<whitequark> ^ I also found and fixed two bugs, one of which would have potentially been a nightmare to fix
<whitequark> annnnnnnd the moment of truth
<GitHub> [artiq] whitequark commented on issue #569: Runtime has been migrated to Rust. https://github.com/m-labs/artiq/issues/569#issuecomment-277428626
<bb-m-labs> build #1312 of artiq is complete: Failure [failed lit_test] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1312 blamelist: whitequark <whitequark@whitequark.org>
GitHub177 has joined #m-labs
<GitHub177> si5324_test/master 2e205af Sebastien Bourdeauducq: switch firmware version to 62.5MHz
GitHub177 has left #m-labs [#m-labs]
<GitHub177> si5324_test/master c1ba566 Sebastien Bourdeauducq: also use same SMAs for gateware version
<GitHub177> si5324_test/master 95808c1 Sebastien Bourdeauducq: increase delay between skew changes
<GitHub177> [si5324_test] sbourdeauducq pushed 3 new commits to master: https://github.com/m-labs/si5324_test/compare/0d06306cfdd4...2e205af2a3e0
<larsc> rjo: what should I call it? the M-Labs JESD204B core?
sandeepkr_ has quit [Remote host closed the connection]
mumptai has joined #m-labs
mumptai_ has joined #m-labs
mumptai_ has quit [Remote host closed the connection]
sandeepkr has joined #m-labs
kuldeep_ is now known as kuldeep
<whitequark> rjo: uhm
<whitequark> I've implemented this optimization
<whitequark> it made test_pulse_rate insignificantly faster and *pessimized* test_pulse_rate_dds
<whitequark> new rtio_output: https://hastebin.com/ayopofucag.css
sandeepkr has quit [Remote host closed the connection]
sandeepkr has joined #m-labs
<whitequark> rjo: I've implemented three more variations of this optimization
<whitequark> (none of which affect rtio_output itself)
<whitequark> initial: size 334868 pulse_rate 5.73e-07 pulse_rate_dds 5.95e-06
<whitequark> rtio+nosig: size 334692 pulse_rate 5.76e-07 pulse_rate_dds 6.30e-06
<whitequark> rtio: size 334692 pulse_rate 5.66e-07 pulse_rate_dds 6.30e-06
<whitequark> full: size 333732 pulse_rate 5.67e-07 pulse_rate_dds 6.65e-06
<whitequark> full+nosig: size 333908 pulse_rate 5.65e-07 pulse_rate_dds 6.45e-06
<whitequark> "rtio" means it's confined to rtio registers only. "nosig" means it avoids a particular corner case
<whitequark> the results are kinda noisy.
<whitequark> but what I conclude is that pulse_rate basically isn't affected by this (it hovers between .65 and .75 regardless) and pulse_rate_dds always regresses
<whitequark> I don't get it
<sb0> larsc, sounds good
<bb-m-labs> build #1313 of artiq is complete: Failure [failed lit_test] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1313 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<sb0> whohoo! the DRTIO bug is gone
<GitHub> [artiq] sbourdeauducq commented on issue #562: Packet corruption bug fixed. https://github.com/m-labs/artiq/issues/562#issuecomment-277440448
<sb0> rjo, can you remind me of those notes you took about the different drtio frequencies and how the transceivers should be configured?
<sb0> oh, the si5324's really hate it when you send garbage into their clock input
<sb0> this is probably what is causing the lock issues
<sb0> the "automatic hitless switching" only works correctly when you either have a clean clock or nothing at the input
<sb0> otherwise, mayhem ensues
<sb0> they can even disable their output completely
sb0 has quit [Quit: Leaving]
<GitHub> [artiq] whitequark closed issue #667: poor codegen for rtio_output https://github.com/m-labs/artiq/issues/667
sandeepkr has quit [Ping timeout: 240 seconds]
<larsc> first question was whether there are open-source HDL cores available
<larsc> I didn't too much time so I put M-labs core under additional references for post-talk study
<GitHub> [artiq] jordens commented on issue #667: Doesn't this indicate that there is a bigger bug somewhere else? https://github.com/m-labs/artiq/issues/667#issuecomment-277455429
<GitHub> [artiq] whitequark commented on issue #667: @jordens Maybe, depending on how you define "bug". As @sbourdeauducq has mentioned elsewhere the root cause of this could be cache aliasing. Unfortunately MiSoC CPU &c cores do not currently provide any insight into their operation--there are no performance counters or anything. The most I could do is a sampling profiler ... https://github.com/m-labs/artiq/issues/667#issuecomment-277455904
<GitHub> [artiq] whitequark commented on issue #667: @jordens Maybe, depending on how you define "bug". As @sbourdeauducq has mentioned elsewhere the root cause of this could be cache aliasing. Unfortunately MiSoC CPU &c cores do not currently provide any insight into their operation--there are no performance counters or anything. The most I could do is a sampling profiler ... https://github.com/m-labs/artiq/issues/667#issuecomment-277455904
<GitHub> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/f94028b8df80239b0c69dce4cfbdc409c2d6d5e7
<GitHub> artiq/master f94028b whitequark: Fix c39394b.
<bb-m-labs> build #398 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/398 blamelist: whitequark <whitequark@whitequark.org>
<bb-m-labs> build #1314 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1314 blamelist: whitequark <whitequark@whitequark.org>
<GitHub74> [rust] whitequark fast-forwarded master from 6abe648 to e4eea73: https://github.com/m-labs/rust/compare/6abe64871e6e...e4eea733065e
<GitHub102> rust/artiq-1.17.0 948f42b whitequark: Add mini-libc (only works on OR1K).
<GitHub102> rust/artiq-1.17.0 d8ded0b whitequark: Add #[cfg(target_family="none")] support to libpanic_*.
<GitHub102> rust/artiq-1.17.0 3466340 whitequark: Remove LLVM submodule.
<GitHub102> [rust] whitequark created artiq-1.17.0 (+4 new commits): https://github.com/m-labs/rust/compare/3466340b412f^...d17512f0337b
<GitHub> [conda-recipes] whitequark pushed 1 new commit to master: https://github.com/m-labs/conda-recipes/commit/5ae7a1bd05335fa97c96b00950e7e8729f413d34
<GitHub> conda-recipes/master 5ae7a1b whitequark: rustc: bump to 1.17.0.
<whitequark> bb-m-labs: force build --props=packages=rustc conda-lin64
<bb-m-labs> build #274 forced
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #274 of conda-lin64 is complete: Exception [exception conda_build] Build details are at http://buildbot.m-labs.hk/builders/conda-lin64/builds/274
<whitequark> bb-m-labs: force build --props=package=rustc conda-lin64
<bb-m-labs> build #275 forced
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #275 of conda-lin64 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/conda-lin64/builds/275
bentley` has quit [Remote host closed the connection]
bentley` has joined #m-labs
mumptai has quit [Quit: Verlassend]