sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<larsc> is there a way to constrain the result of a expression in verilog to a certain width
<larsc> except for using a wire
<larsc> e.g. a + b and I want the result to be 8 bits
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<cr1901_modern> larsc: I don't think so. Can you bitmask the result and hope the optimizer removes the uneeded wires?
<cr1901_modern> Or just not connect them?
<larsc> cr1901_modern: what I was trying was {a,b}; where a and b are expressions
<larsc> for this to work they need to be fixed width
<larsc> masking might work
<larsc> it works!
<larsc> wire [10:0] foo = {('d7 + 'd1) & {4{1'b1}}, ('d9 - 'd2) & {8{1'b1}}};
<larsc> not pretty, but effectice, thanks
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<cr1901_modern> larsc: You're welcome but it was just a guess :P.
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