sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> whitequark, any progress on background RPCs?
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<GitHub26> [artiq] jordens pushed 4 new commits to phaser: https://git.io/vXk26
<GitHub26> artiq/phaser 6d07a16 Robert Jordens: Merge branch 'master' into phaser...
<GitHub26> artiq/phaser 8eff858 Robert Jordens: moninj.rs: force u32 dds_ftws
<GitHub26> artiq/phaser 2a1e529 Robert Jordens: phaser: DDS config dummies
<whitequark> sb0: I promptly got sick with flu after landing in RU, though I have some prototype working already
<rjo> whitequark: i just hit the issue i filed (https://github.com/m-labs/artiq/issues/598). could you have a look?
<whitequark> let's see
<whitequark> yes, that does seem related to the amount of code
<rjo> well. not if you are stricken down with flu
<whitequark> i feel better already anyway...
<rjo> whitequark: ok. could you also quickly confirm that the two commits in phaser after the master merge are "correct" (or at least needed as a work around for now)
<rjo> i.e. 8eff858 and 2a1e529
<whitequark> yes, seems ok
<rjo> whitequark: ack.
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<sb0> sigh, the mentor graphics garbage just crashes on startup in wine
<sb0> pretty sure the DRM crippleware would be the next issue if it didn't anyway
<sb0> rjo, what about the artiq-hardware repos?
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<rjo> i tried wine and it doesn't look easy either. (they actually bundle wine....)
<rjo> sb0: i'll roll that thing back when greg has committed to sinara.
<sb0> ah I was trying visECAD, which is windows-only
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<whitequark> rjo: ImportError: No module named 'jesd204b'
<whitequark> I've updated misoc and migen already
<whitequark> that's on phaser branch
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<whitequark> rjo: cargo/or1k-unknown-none/debug/libksupport.a(ksupport.0.o):(.data.rel.ro.ref4384+0x380): undefined reference to `ad9154_init'
<whitequark> hm
<whitequark> oh I should be using the phaser gateware
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<rjo> whitequark: also use the other/aux kc705. i can see a few problems with the phaser gateware on the buildbot kc705.
<rjo> "can see" in the sense of "i'd be worried about"
<whitequark> ack
<sb0> rjo, I'm not sure about the "low noise" clocking plan. are we just using another PLL on Sayma instead of the one built into the 7044, or do we distribute 2.4GHz from an off-crate oscillator into the RF backplane?
<whitequark> rjo: somethings screwy with the DNS
<whitequark> $ ping kc705aux
<whitequark> PING web.serverraum.org (213.133.101.245) 56(84) bytes of data.
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<whitequark> rerunning dhclient fixed that
<whitequark> now kc705aux simply has no record...
<whitequark> rjo: what's its IP?
<rjo> whitequark: yes. i don't know how you git that to work for the other kc705. ip is ends in 51
<whitequark> rjo: oh. i went into the openwrt configuration thing and added a static hostname
<rjo> whitequark: iirc i did that.
<whitequark> hrm
<rjo> sb0: we are using a 100->2000 MHz pll on sayma (the lock mezzanine) that's (significantly) better than a HMC7044. and we have the option of ignoring the pll mezzanine on sayma and feedint 2 GHz directly into the hmc7044/3.
<rjo> there is no high frequency on the backplane IIRC.
<rjo> whitequark: the dns setup is a bit weird. having lab.m-labs.hk be a public record _and_ having private hosts under that is tricky IME.
<rjo> because you'd want the search domain to be lab.m-labs.hk then.
<rjo> but anyway. that's a minor issue.
<whitequark> rjo: cat /etc/resolv.conf
<whitequark> that's exactly how it's set up
<whitequark> anyway uh I seem to be able to run $ artiq_run artiq/examples/phaser/repository/test_ad9154_status.py ?
<rjo> whitequark: then something changed. before it was frequently hitting the public wildcard cname.
<whitequark> rjo: there seems to be some problem where that resolv.conf is replaced with the IPv6 name of the router
<rjo> whitequark: let me check my toolchain versions...
<whitequark> rjo: hang on. it doesn't seem to poke the right kc705
<whitequark> ok I see, which ttyUSB is kc705aux on?
<rjo> whitequark: #/dev/serial/by-id/usb-Silicon_Labs_CP2103_USB_to_UART_Bridge_Controller_0001-if00-port0
<whitequark> rjo: how do I reset it?
<sb0> rjo, ok. what PLL chip is that?
<rjo> sb0: that's (the clock/pll mezzanine) the design oxford is doing. don't remember details.
<rjo> whitequark: with openocd.
<rjo> whitequark: assuming you mean loading a bitstream into that kc705.
<rjo> whitequark: i can load mine and you can have a go at it if you want.
<rjo> whitequark: "source [find board/kc705.cfg]; ftdi_serial 210203A031AB; ..."
<whitequark> I reset it using openocd
<rjo> whitequark: just fyi: the bitstream and runtime in flash are outdated. but i guess you flashed yours, right?
<whitequark> I don't build or flash a bitstream because it's extremely slow over here
<rjo> whitequark: then you load them dynamically. that's what i do as well.
<whitequark> no, I mean building mostly.
<rjo> whitequark: ok. just don't use the bitstream/runtime that i had in that flash.
<whitequark> rjo: can you flash yours?
<whitequark> that would save me the bother of building it myself, downloading vivado, etc
<rjo> whitequark: sure. will do now.
<rjo> whitequark: flash or just load?
<rjo> whitequark: will flash
<rjo> whitequark: done
<whitequark> thanks
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<whitequark> rjo: unable to reproduce
<whitequark> rjo: fascinatingly
<whitequark> I am able to reproduce that, but *only* when artiq_run'ing from the lab.
<whitequark> no LoadLibrary ever arrives