04:37 <GitHub112> [artiq] whitequark pushed 1 new commit to master: https://git.io/vPq0j

04:37 <GitHub112> artiq/master 30e997f whitequark: Rust: implement idle kernels and session takeover.

04:57 <bb-m-labs> build #89 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/89

04:59 <bb-m-labs> build #980 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/980 blamelist: whitequark <whitequark@whitequark.org>

08:58 <_florent_> rjo: thanks, I'm testing with _SPI_ in the AD9154_REF_CLK_DIVIDER_LDO bits, not better for now. For now I'm using a 2Gbps linerate.

08:59 <_florent_> rjo: I'll port to misoc/migen as soon as I have something working, but if you want I can provide you the phy usable with misoc/migen easily. (If you want to also do tests on your side on CGS)

09:21 <key2> hey, anyone has tried the lm32 debugger ?

09:46 <_florent_> rjo: I'm able to get the SERDES PLL to lock by using the exact example startup sequence from the datasheet:

09:46 <_florent_> rjo: https://github.com/enjoy-digital/litejesd204b-ad9154-demo/commit/2b1de6fa6f4bc028cba0c2a82d98242c27eab393

09:47 <_florent_> rjo: I'll use that to understand what we are doing wrong in the startup sequence

10:14 <rjo> _florent_: ack. if you can port the PhyTX and the CoreTX then I could start the integration into artiq/phaser. might do some testing as well.

10:15 <rjo> _florent_: ok. that's with the dac pll.

10:15 <rjo> _florent_: that datasheet is not really written all that clearly w.r.t. how do configure it when not using the dacpll etc. where the individual dividers are etc.

12:50 <GitHub3> [artiq] jordens pushed 4 new commits to phaser: https://git.io/vPqMY

12:50 <GitHub3> artiq/phaser 8076581 Robert Jordens: sawg: missing import

12:50 <GitHub3> artiq/phaser 5b1f562 Robert Jordens: ad9154: addrinc, recal serdes pll

12:50 <GitHub3> artiq/phaser 9e77861 Robert Jordens: phaser: coredevice, example tweaks

13:31 <sb0> whitequark, a timer interrupt, what for?

13:34 <sb0> _florent_, btw why exactly didn't you use migen in the first place?

16:26 <_florent_> sb0: to use litescope and the debug feature I have in my fork

16:28 <_florent_> rjo: I'm going to port the code to misoc/migen tomorrow morning so that you can start integrating things and will continue debugging after

20:18 <whitequark> sb0: checking for threads that don't voluntarily yield

20:18 <whitequark> it's easy to accidentally make those; I got bitten by that twice already

20:18 <whitequark> if it's easy to get a timer interrupt then that would be a nice convenient fix

20:19 <rjo> whitequark: hey. before i dig deeper, what's --kernel-addr for flterm with artiq? just 0x40000000?

20:21 <whitequark> I don't really ever specify it, but yes. runtime : ORIGIN = 0x40000000

20:23 <rjo> ack.

20:25 <rjo> larsc: AD datasheets are mysterious things... there is a very prominent (and extremely relevant) deviceclock mux in ad9144 ..52 and ..54 (e.g. http://www.analog.com/media/en/technical-documentation/data-sheets/AD9144.pdf page 4).

20:25 <rjo> larsc: that mux switches with "CLK_SEL". but there is no reference to that bit/register anywhere in the datasheet.

20:27 <rjo> larsc: and even worse, assuming it's just a naming issue, I can not find any other register that would perform that very function of bypassing the pll and driving the device directly from deviceclock. this is certainly a mode that is frequently praised throughout the datasheet. but it's unclear to me how to enable it.

20:28 <rjo> and while browsing. i found a "PrJ" revision datasheet, that lists lots of "secret" registers that are not listed in later datasheet version.

20:30 <rjo> and i found https://github.com/analogdevicesinc/no-OS/blob/master/drivers/ad9144/ad9144.h which references those registers. Nice things like "Customer Operating Mode.".

20:44 <rjo> oh i love that. the "preliminary technical data"-sheets are so much better than the final ones...