sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub106> [artiq] whitequark pushed 1 new commit to master: https://git.io/vPiNF
<GitHub106> artiq/master 6da1f39 whitequark: runtime: fix use of $(realpath) in Makefile.
<bb-m-labs> build #118 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/118 blamelist: whitequark <whitequark@whitequark.org>
<bb-m-labs> build #1012 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1012 blamelist: whitequark <whitequark@whitequark.org>
<GitHub193> [rust] whitequark pushed 1 new commit to artiq: https://github.com/m-labs/rust/commit/e487020f9317afeb0182a6fc3c0c3152aea66996
<GitHub193> rust/artiq e487020 whitequark: Add support for LLVM libunwind.
<GitHub35> [conda-recipes] whitequark pushed 1 new commit to master: https://github.com/m-labs/conda-recipes/commit/29ad40e2994859272d7a03fd0c20a26bebf44981
<GitHub35> conda-recipes/master 29ad40e whitequark: rust-core-or1k: bump.
<whitequark> bb-m-labs: force build --props=rust-core-or1k conda-lin64
<bb-m-labs> Something bad happened (see logs)
<whitequark> bb-m-labs: force build --props=package=rust-core-or1k conda-lin64
<bb-m-labs> build forced [ETA 2m46s]
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #232 of conda-lin64 is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/conda-lin64/builds/232
<whitequark> bb-m-labs: force build --props=package=rust-core-or1k conda-lin64
<bb-m-labs> build forced [ETA 2m46s]
<bb-m-labs> I'll give a shout when the build finishes
<GitHub76> [conda-recipes] whitequark force-pushed master from 29ad40e to 0f9b600: https://github.com/m-labs/conda-recipes/commits/master
<GitHub76> conda-recipes/master 0f9b600 whitequark: rust-core-or1k: bump.
<bb-m-labs> build #233 of conda-lin64 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/conda-lin64/builds/233
<whitequark> bb-m-labs: force build artiq
<bb-m-labs> build #1013 forced
<bb-m-labs> I'll give a shout when the build finishes
<GitHub3> [migen] whitequark pushed 2 new commits to master: https://git.io/vPihC
<GitHub3> migen/master 7427eee whitequark: lattice: add IceStormProgrammer.load_bitstream.
<GitHub3> migen/master 41c4920 whitequark: platforms: add Lattice iCE40-HX8K-B-EVN.
<bb-m-labs> build #119 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/119
<bb-m-labs> build #92 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/92
<bb-m-labs> build #143 of misoc is complete: Exception [exception interrupted] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/143
<bb-m-labs> build #1013 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1013
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<whitequark> hmmm, test_pulse_rate_dds regressed O_o
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<GitHub133> [migen] whitequark pushed 2 new commits to master: https://git.io/vPPL6
<GitHub133> migen/master 9cd4900 whitequark: doc: add documentation for FSM module.
<GitHub133> migen/master 33cf38d whitequark: doc: use sphinx_rtd_theme.
<bb-m-labs> build #93 of migen is complete: Failure [failed make_doc] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/93 blamelist: whitequark <whitequark@whitequark.org>
<bb-m-labs> build #144 of misoc is complete: Exception [exception interrupted] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/144
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<GitHub40> [buildbot-config] whitequark pushed 1 new commit to master: https://github.com/m-labs/buildbot-config/commit/190b91a2d9d30c09023316950fe94f695ff988d4
<GitHub40> buildbot-config/master 190b91a whitequark: Update migen build factory to fix doc build.
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<whitequark> bbb
<whitequark> bb-m-labs: force build migen
<bb-m-labs> build #94 forced
<bb-m-labs> I'll give a shout when the build finishes
<GitHub97> [migen] sbourdeauducq pushed 1 new commit to master: https://git.io/vPPt3
<GitHub97> migen/master 20ef480 Sebastien Bourdeauducq: migen/sim: support special_overrides
<bb-m-labs> build #95 of migen is complete: Exception [exception deploy_doc] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/95 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #94 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/94
<bb-m-labs> build #145 of misoc is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/145
<whitequark> this looks good to you?
<sb0> yes. but states need not be strings.
<GitHub21> [misoc] sbourdeauducq pushed 4 new commits to master: https://git.io/vPPt1
<GitHub21> misoc/master 1d42e61 whitequark: i2c: copy from drtio_transceiver_test
<GitHub21> misoc/master cb3fa41 Sebastien Bourdeauducq: spi: reorganize
<GitHub21> misoc/master 3ff55da Sebastien Bourdeauducq: test_i2c: do not break migen
<bb-m-labs> build #146 of misoc is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/146 blamelist: whitequark <whitequark@whitequark.org>, Sebastien Bourdeauducq <sb@m-labs.hk>
<GitHub70> [migen] whitequark pushed 1 new commit to master: https://git.io/vPPt5
<GitHub70> migen/master c43fb67 whitequark: doc: clarify FSM doc.
<bb-m-labs> build #96 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/96
<bb-m-labs> build #147 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/147
<bb-m-labs> build #120 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/120
<bb-m-labs> build #1014 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1014
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<GitHub71> [artiq] sbourdeauducq pushed 1 new commit to master: https://git.io/vPPOC
<GitHub71> artiq/master 8583497 Sebastien Bourdeauducq: gateware/spi: fix import
<GitHub128> [artiq] sbourdeauducq pushed 1 new commit to phaser: https://git.io/vPPOW
<GitHub128> artiq/phaser b600252 Sebastien Bourdeauducq: gateware/spi: fix import
<whitequark> why am I getting KeyError: "Unresolved clock domain: 'sys'" here ?
<sb0> what do you want it to do?
<sb0> the default clock generator in the platform can only handle one clock domain
<sb0> you have to redefine it if you do anything else
<whitequark> ah, hm
<whitequark> how do I do that?
<whitequark> ah I see, the code in finalize()
<whitequark> maybe I shouldn't use clock domains for this anyway
<bb-m-labs> build #121 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/121
<bb-m-labs> build #1015 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1015 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<whitequark> sb0: the platform.request() API is incredibly bad.
<sb0> what do you propose?
<whitequark> something with less moving parts. I can't say what exactly since I haven't understood all of the use cases yet
<whitequark> but the existing API is very frustrating to use.
<whitequark> at the very least it shouldn't outright remove stuff from self.available, it should mark that as used.
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<sb0> so, in what case in particular is it frustrating?
<whitequark> so it's three things
<whitequark> first, the way it treats nonexistent pin groups and already used pin groups the same
<whitequark> second, the four different levels in the tree
<whitequark> i.e. name, number, subsignals, and bits within a signal/subsignal
<whitequark> third, that it's undocumented
<whitequark> actually, fourth, that the error message mention ":None" or whatever
<whitequark> so when it doesn't work, you have no idea what's broken and how to fix it
<whitequark> do I pass "GPIO0:10" into it? the message suggests that syntax but it's of course wrong
<cr1901_modern> +1. I've run into the fourth problem many times before
<sb0> how would you change the representation to avoid those four levels?
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<whitequark> how do subsignals work?
<sb0> as for your other critiques, it's been simple enough for me that I haven't had issues with its primitive error messages
<whitequark> because you wrote it, yes.
<sb0> "subsignals" are just for creating grouped signals
<sb0> you request the group, and you get a bag of related signals
<sb0> e.g. for sdram, you do not want to request address and data pins separately, since one practically cannot be used without the other
<sb0> and passing them around one by one would otherwise be messy
<whitequark> hrm
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<GitHub86> [artiq] sbourdeauducq pushed 2 new commits to master: https://git.io/vPPdW
<GitHub86> artiq/master 6909969 Sebastien Bourdeauducq: doc: clarify usage of pause/check_pause, closes #571
<GitHub86> artiq/master 02adccf Sebastien Bourdeauducq: dashboard/datasets: use scientific spinbox and increase number of decimals, closes #572
<GitHub83> [artiq] sbourdeauducq pushed 2 new commits to release-2: https://git.io/vPPd4
<GitHub83> artiq/release-2 115204f Sebastien Bourdeauducq: dashboard/datasets: use scientific spinbox and increase number of decimals, closes #572
<GitHub83> artiq/release-2 5ecfa81 Sebastien Bourdeauducq: doc: clarify usage of pause/check_pause, closes #571
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<GitHub135> [misoc] sbourdeauducq pushed 1 new commit to master: https://git.io/vPPFV
<GitHub135> misoc/master 9f471a1 Robert Jordens: cordic: copy from artiq/phaser
<bb-m-labs> build #122 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/122
<bb-m-labs> build #148 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/148
<bb-m-labs> build #1016 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1016 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<bb-m-labs> build #123 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/123
<bb-m-labs> build #1017 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1017
<whitequark> sb0: does migen support asynchronous reset?
<sb0> no. why do you need asynchronous reset?
<whitequark> well, one of my old designs used an asynchronous reset
<whitequark> it might not actually have needed that
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<whitequark> sb0: migen doesn't guard against trying to set the same thing in comb and sync simultaneously?
<sb0> no
<sb0> but ise/vivado will spot that
<whitequark> yosys doesn't (and it's by design)
<sb0> so what logic does it infer in this case?
<whitequark> it appears the combinatorial part is ignored
<sb0> and how is that a good design decision?
<whitequark> it isn't
<whitequark> the "by design" part refers to the "if you want your verilog checked, use iverilog" approach yosys has
<sb0> but in event-driven verilog like iverilog does, driving from both comb and sync is valid.
<whitequark> hm
<whitequark> I'll file a bug then
<whitequark> actually, no, it emits a warning in my testcase.
<whitequark> I wonder why that didn't show up with migen-generated code
<whitequark> weird, it shows up now. but it compiled earlier...
<sb0> whitequark, http://www.minicircuits.com/pdfs/HT-4-SMA.pdf << how come you don't have this device yet? :-)
<whitequark> sb0: oh great, I was looking for something like that just a while ago
<whitequark> I hate unscrewing SMAs
<whitequark> have you ordered that yet?
<sb0> I haven't
<whitequark> that's just $25
<whitequark> never having to fiddle with that shit again: priceless
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<sb0> _florent_, can you look into https://github.com/m-labs/misoc/issues/39 ?
<sb0> whitequark, https://github.com/m-labs/artiq/commit/f10a4498c7ff8e39a39ad51eea45b21b45e22563 < this should go on release-2 as well, right?
<sb0> anything else that should be there? I didn't follow all the commits since those were mostly rust
<whitequark> sb0: no
<sb0> no to which question?
<whitequark> first
<sb0> ok
<whitequark> watchdog_set used to take int
<whitequark> I made it long long because the runtime does that
<whitequark> (both the C runtime did, and the Rust runtime does; but only in the Rust ksupport this change is)
<sb0> rjo, what is the jsync ttl for?
<rjo> watching subclass 1 synchronization.
<sb0> ok... can we at least remove ttl_serdes_7series.Input_8X?
<rjo> sb0: we need that for sysref timestamping.
<sb0> it could stay in the phaser branch until idelay scan is implemented, but otherwise make no plans to support input-only TTLs
<rjo> can idelay cover 8ns?
<sb0> combined with a serdes, yes
<rjo> input-only ttls are needed for IOStandard reasons here.
<sb0> my point is: the idelay scan will be a completely independent design, which won't touch anything rtio
<sb0> and that design won't attempt to use the pin as output, of course
<rjo> sure. in the final design sysref doesn't need to go through rtio.
<sb0> btw, as an alternative to idelay we can also use a mmcm fine phase adjust, which doesn't have tap calibration issues
<rjo> ack. that dynamic runtime reconfig stuff nice?
<sb0> unlike the pll, the mmcm has convenient fine phase adjust signals that don't require mucking with obscure xilinx reconfig details
<sb0> the phase adjust is also 7x more precise
<rjo> sounds good.
<rjo> sb0, whitequark, _florent_: ok to re-license artiq as LGPLv3+?
<whitequark> rjo: does that rule out using picotcp for sure?
<rjo> whitequark: it would. unless i can get them to go LGPL as well.
<sb0> ok
<rjo> whitequark: well. maybe technically and with copious amounts of hair-splitting one could separate the runtime+picotcp and make that gpl...
<whitequark> no, that's harder than integrating the other runtime
<whitequark> the other stack*
<whitequark> okay. then we're going with brian's stack
<rjo> whitequark: ack. is that a choice that you want to make now or does it make sense to at least try to get the tass-belgium guys to go the same route?
<whitequark> rjo: let's ask them first.
<rjo> whitequark: ack will do.
<whitequark> thanks
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