sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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* cr1901_modern notices m-labs acct retweeted the RISC-V dev board tweet, despite it looking "pretty disappointing" :D
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<rjo> whitequark: are the esp* working?
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<rjo> _florent_: and if i leave enable=0 it should be able to get CODEGRPSYNCFLG=0x0f, right?
<_florent_> rjo: disabling the core generate put the phy/link/transport in reset
<_florent_> rjo: to get CODEGRPSYNCFLG=0xf you need to enable the core
<_florent_> rjo: I'm testing the outputs now, for now that's not working
<rjo> _florent_: ah. ok.
<rjo> _florent_: then we need to break this up a little. a proper initialization sequence goes lock-step: emit K, setup DAC for SERDES PLL lock, verify lock, setup DAC for CGS, verify CGS, verify SYNC, only then do ILAS, etc.
<rjo> but that's for later.
<rjo> _florent_: at least the stpl works for me as well.
<_florent_> rjo: I'm not sure we can break up this that much:
<_florent_> rjo you don't neet to emit data to get the SERDES PLL to lock, it's just related to the input clock
<_florent_> rjo: so we can do that with the FPGA reseted
<_florent_> rjo: we then enable the core, it start sending K28.5 for CGS, the DAC released SYNC when it sees K28.5 on all lanes, the core then have to send ILAS on the next LMFC after SYNC is released
<rjo> _florent_: the serdes pll will lock even with the phy reset?
<_florent_> rjo: yes
<rjo> _florent_: ok. but still. there needs to be a way to do CGS without the entire thing then falling into ILAS.
<rjo> _florent_: e.g. to do the checks as in table 89
<_florent_> rjo: yes, for that we just have to disconnect the jesd_sync from the start of the core
<rjo> _florent_: ack.
<_florent_> rjo: but yes, we'll add more control registers
<_florent_> rjo: are you aware of specific registers I can check to be sure the digital datapath/outputs are working correctly (I'm going to read the datasheet for these points)
<rjo> _florent_: by the way, i assume that you are outputting an AC signal for you test, right?
<rjo> _florent_: the way i am setring them up is correct. you are doing the same.
<rjo> _florent_: at least afaik
<_florent_> rjo: I'm outputing a counter (ramp) with different increments for each converter
<rjo> _florent_: ok. that's good. just want to make sure that you are not eaten by the baluns.
<_florent_> rjo: ok.
<GitHub117> [artiq] jordens pushed 3 new commits to phaser: https://git.io/vPgwm
<GitHub117> artiq/phaser 1117fe1 Robert Jordens: phaser: support core stpl
<GitHub117> artiq/phaser 3b1d5d7 Robert Jordens: phaser: verify flags in dac_setup
<GitHub117> artiq/phaser f515c11 Robert Jordens: phaser: fix refclk period spec
<rjo> _florent_: i noticed yesterday that the softreset doesn't really do much at all. most registers still hold the same data.
<_florent_> rjo: same here
<rjo> that's bad.
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<_florent_> rjo: I have something on the outputs
<_florent_> rjo: by only keep the first 2 lines of the digital path configuration
<_florent_> rjo: I'm still trying to understand what I'm seeing, but frequencies ratios between channels seems to correspond to what I'm injecting
<rjo> _florent_: ok. the rest should actually be NOPs, the same as the defaults.
<_florent_> rjo: it seems it's not then :)
<rjo> _florent_: yes.
<rjo> _florent_: i'll check those registers
<_florent_> rjo: ok thanks, I just keep these 2 first lines for now
<rjo> _florent_: ack
<rjo> _florent_: digital gain must not be off. that's the one.
<_florent_> rjo: ok thanks
<GitHub97> [artiq] jordens pushed 5 new commits to phaser: https://git.io/vPgbu
<GitHub97> artiq/phaser 3f1d96b Robert Jordens: phaser: tweak dac_setup
<GitHub97> artiq/phaser 466d1e8 Robert Jordens: phaser: update stpl
<GitHub97> artiq/phaser 5f737be Robert Jordens: phaser: 500 MHz dacclock
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<_florent_> rjo: are you doing some tests?
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<_florent_> rjo: if so, I'm doing some on my side, I'm wondering if the behaviour I have is not related to byte ordering on the converter sample, I'm investigating on that
<rjo> _florent_: i would if i had a working scope.
<_florent_> rjo: ah ok
<rjo> _florent_: the setup is in HK, im am in DE.
<rjo> _florent_: what behavior.
<rjo> ?
<rjo> _florent_: i keep having problems with sync.
<rjo> _florent_: this is either very flaky or i am doing something veyr wrong.
<_florent_> rjo: what's your problem with sync?
<rjo> _florent_: same as last week. it doesn't lock.
<_florent_> rjo: behaviour: I'm generating a ramp but I'm more seeing some spikes than a real ramp. But that's maybe due to the baluns.
<_florent_> rjo: at least frequency seems to be fine on each channel
<rjo> _florent_: which frequency?
<rjo> "what" frequency?
<rjo> you should be able to make a good ramp if your fundamental ramp frequency is > 1 MHz and < maybe 20 MHz.
<rjo> but you should see edges from the 250 MHz dac sampling rate.
<rjo> ah. no. minimum is more like 8 MHz.
<rjo> whitequark, sb0: if either of you makes it to the lab, please let me know.
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<GitHub34> [artiq] enjoy-digital pushed 1 new commit to phaser: https://git.io/vP2ff
<GitHub34> artiq/phaser 12b8598 Florent Kermarrec: stpl: fix byte ordering
<_florent_> rjo: I just fix a byte ordering issue in the transport layer
<GitHub136> [artiq] jordens pushed 3 new commits to phaser: https://git.io/vP2fn
<GitHub136> artiq/phaser 0d1ed24 Robert Jordens: phaser: tweak sawg example
<GitHub136> artiq/phaser 9880b1e Robert Jordens: phaser: update README
<GitHub136> artiq/phaser 2d14864 Robert Jordens: Revert "phaser: 500 MHz dacclock"...
<_florent_> rjo: it seems fine here, signal is not very clean, but that's maybe due to my scope
<rjo> _florent_: looks good. i have the DDS's already tested. don't need a pattern there. do you have a screenshot?
<_florent_> rjo: going to make one
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<GitHub81> [misoc] jordens tagged 0.4 at master: https://git.io/vP2k9
<bb-m-labs> build #139 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/139
<GitHub123> [artiq] jordens pushed 1 new commit to master: https://git.io/vP2Ia
<GitHub123> artiq/master 290498a Robert Jordens: conda: misoc 0.4 (csr)
<GitHub4> [artiq] jordens pushed 2 new commits to phaser: https://git.io/vP2LO
<GitHub4> artiq/phaser 370b05d Robert Jordens: phaser: README: specify versions
<GitHub4> artiq/phaser 9c8b21b Robert Jordens: phaser: let link settle a bit longer before starting
<sb0> rjo, what do you need?
<whitequark> reboot the scope, which is hung
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<rjo> _florent_: looks fine. i'd attribute it to the dc bias and your scope being limited at < 200 MHz distorting stuff.
<rjo> sb0: yes. reboot the scope. thanks!
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<bb-m-labs> build #113 of artiq-board is complete: Exception [exception interrupted] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/113
<bb-m-labs> build #1004 of artiq is complete: Exception [exception] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1004
<rjo> sb0: or even better, could you also power-cycle the kc705 with the AD9154?
<sb0> okay I'll do that tomorrow afternoon if whitequark doesn't get to it before
<whitequark> I have an appointment tomorrow morning so I'll be able to do that maybe at 1000 HKT
<rjo> whitequark: ack
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<bb-m-labs> build #1005 of artiq is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1005 blamelist: Robert Jordens <rj@m-labs.hk>
<GitHub17> [artiq] jordens force-pushed phaser from 370b05d to 81511fe: https://git.io/vi7qh
<GitHub17> artiq/phaser 81511fe Robert Jordens: phaser: README: specify versions
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<GitHub86> [artiq] klickverbot opened pull request #584: language: Add "A" (ampere) as well-known unit for arguments (master...ampere-unit) https://git.io/vPa8i
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