sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<whitequark>
sb0: any idea how many spartan 3e slices will mor1kx take?
<cr1901_modern>
whitequark: How big of a spartan 3e? I'm not sure how wonderful of a comparison it is, but LM32 will not fit on an XC3S200A without concessions such as reducing cache size (Not a block RAM problem, of course)
<whitequark>
xc3s500
<cr1901_modern>
Is this for adding another ARTIQ target?
<sb0>
maybe 50%
<sb0>
what are you doing with such an antiquated device?
<cr1901_modern>
^ That's a question you normally ask me :P
<whitequark>
I don't
<whitequark>
someone else has just that board and wonders if they can run or1k on it
<cr1901_modern>
I did a rough calculation before: 200A is about 4/9 the size of an LX9 (not accounting for 6-input vs 4-input LUT). MiSoC design fits fine on an LX9, so a 500E, assuming the LUTs are the same, should fit fine.
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<rjo>
whitequark: pdq has a 3a500e. i (very briefly) looked at putting a lm32 on there a while ago and did not succeed.
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<whitequark>
huh, really?
<whitequark>
I've dug up some #milkymist logs earlier and apparently lm32 is half as big as or1k and or1k takes 1700 slices...
<whitequark>
and 3a500e has 4600 or so
<whitequark>
that sounds weird
<rjo>
i added it onto a design that uses a bit of the fpga. i seem to remember that lut's wasn't the limit but bram. i would guess that if you are fine with spending *most* of the fpga on the cpu then it would be ok.
<whitequark>
ah yes, cr1901_modern mentioned that just above
<whitequark>
the person who wants that will need some bram for four ethernet interfaces
<whitequark>
i suppose. does liteeth use bram?
<sb0>
whitequark, mor1kx has improved since then, it's about the same size as lm32 now
<sb0>
yes, it uses bram
<sb0>
you need to store the packets somewhere (and cannot pause the data stream)
<whitequark>
alright
<whitequark>
I suppose packet buffers could be put into SDRAM
<sb0>
also, you typically want to store two packets, as another one is often coming while the CPU processes the first
<whitequark>
so that's 48kbit per ethif
<whitequark>
for rx buffers alone
<sb0>
you can put them into sdram, but meeting the real-time requirements will need a bit of thought
<sb0>
especially as the SDRAM that a slowtan3e can drive isn't fast to begin with
<sb0>
iirc there aren't even IOSERDESes on this thing, so if you want to run the SDRAM at a decent frequency (>100MHz) you will need to implement that yourself
<whitequark>
I see
<sb0>
and then you get a wide bus that eats your limited resources... well it's a challenge
<sb0>
maybe you can process the ethernet packets in-flight? no CPU, no/little memory
<whitequark>
I'm not sure what they really want...
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<GitHub55>
[artiq] sbourdeauducq pushed 3 new commits to master: https://git.io/visBd
<GitHub55>
artiq/master deb51ea Sebastien Bourdeauducq: gui: update version number in logo
<GitHub55>
artiq/master 524ba80 Sebastien Bourdeauducq: artiq_client: add show ccb