<sb0>
and that's when you drop on the first column. qt fucks up even more when you drop on others.
<sb0>
rjo, i propose moving #40 to 3.0 and releasing 2.0rc1
<sb0>
oh, QTreeWidget does this correctly.
<sb0>
so a workaround without much code is to use QTreeWidget instead of QTableWidget. seems obscure enough that no one has proposed that solution despite dozens of complaints over several years...
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<whitequark>
ok, setting up the scope
<whitequark>
wait, we have three FPGA devboards now?
<whitequark>
what's the third?
<sb0>
KCU105
<sb0>
we may use Kintex Ultrascale on the new ARTIQ hardware
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<whitequark>
sb0: you don't have any jumpers do you?
<whitequark>
rjo: so, which connection between fmc and kc705 for clock is it exactly?
<whitequark>
you didn't mention yesterday, I don't think
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<whitequark>
aha, J1 is the clock input on ad9154-fmc
<whitequark>
rjo: the scope is at 192.168.1.132. the clock connection goes from USER_CLK_P to J1
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<sb0>
whitequark, take a XADC card (which we don't use) from a KC705 box and cannibalize its jumpers.
<sb0>
the KC705 boxes are behind the fridge
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<whitequark>
sb0: too late, I just soldered a wire there
<whitequark>
is picotcp any good? I see it targets stupid architectures like AVR. that is usually a sign of having gross workarounds for their limitations.
<rjo>
whitequark: thanks. also the two jumpers from that note from _florent_? JP3 XP1
<whitequark>
personally I think once we get lwip working, it is worth migrating to rust or not migrating at all
<whitequark>
rjo: yes, JP3 soldered on the board, 5-6 pins XP1 shorted with a wire
<rjo>
whitequark: to me at least picotcp looks _much_ better than lwip. and i have a hard time estimating the amount of work for a sufficiently complete and good rust network stack.
<rjo>
whitequark: ack.
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<rjo>
whitequark: and ethernet hooked up as well on that board?
<whitequark>
uhhh, I don't remember
<whitequark>
can you flash and ping it?
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<rjo>
whitequark: will do
<rjo>
whitequark, sb0: does the buildbot specifically target "its" kc705 when flashing? if not i guess i'll rig up a few openocd patches.
<sb0>
yes, it does
<whitequark>
does it? I thought it just ran artiq_flash
<sb0>
no openocd patch is required
<sb0>
I modified artiq_flash to support this
<whitequark>
oh
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<rjo>
sb0: ack. i'd like to move that into the openocd scripts at some point
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<sb0>
rjo, the scripts don't actually need modification, have a look at the mini-drtio readme
<sb0>
I found this later after I did the buildbot setup.
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<rjo>
sb0: ack. then the --target-file thing is not really needed.
<rjo>
good that that ftdi_ driver is stupid enough.
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<sb0>
rjo, you still need a mechanism in artiq_flash to modify the script passed to openocd.
<rjo>
sb0: the command line arguments. sure.
<rjo>
sb0: why is i2c on that separate wb area and not on the regular csr?
<sb0>
what i2c?
<sb0>
are you asking why the i2c core in mini-drtio is not using the misoc csr generator? whitequark wrote this.
<rjo>
the one for the NIST_QC1 ttl direction switches/drivers
<sb0>
ah? because it is controlled by the kernel CPU.
<sb0>
and that's NIST_QC2
<sb0>
the kernel CPU system does not have a CSR bus
<rjo>
it
<rjo>
's on all of the NIST_Ions ones.
<sb0>
no, QC1 is the old Penning lab rig with the AD9858 and SCSI cables
<rjo>
sb0: no. the i2c core is on all of them.
<sb0>
ah. yes, but it does nothing on the other adapters (except give access to the kc705 internal i2c bus)
<rjo>
but shouldn't we collect all the register_kernel_cpu_csrdevice() things and put them onto one CSR bankarray (for the kernel cpu)
<sb0>
there is no CSR bankarray for wishbone
<sb0>
well, we can add one
<rjo>
i mean add the usual csrbanks-csrbankarray-csr2wishbone chain.
<GitHub0>
artiq/master 9fd9235 Robert Jordens: RELEASE_NOTES: 2.0rc1
<GitHub126>
[artiq] sbourdeauducq pushed 1 new commit to master: https://git.io/viO9n
<GitHub126>
artiq/master 8f6c445 Sebastien Bourdeauducq: gui/applets: support groups, creating and deleting applet groups, renaming groups, moving applets from one group to another and reordering applets and groups via drag-and-drop